From 3d0288d6767fc4b0ddeb270392a22bf1894767cd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 4 Dec 2016 15:39:44 +0200 Subject: intel/i82801dx: Support 2MiB FWH part MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Default setting of southbridge assigned 1MiB of memory for FWH ID 0, while 2MiB is commercially available. Only remap IDs when large ROM is requested in case some board uses multiple FWH parts. Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17918 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Jonathan Neuschäfer Reviewed-by: Arthur Heymans --- src/southbridge/intel/i82801dx/Kconfig | 4 ++++ src/southbridge/intel/i82801dx/bootblock.c | 21 +++++++++++++++++++++ 2 files changed, 25 insertions(+) create mode 100644 src/southbridge/intel/i82801dx/bootblock.c (limited to 'src') diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig index af8300e8ed..82db1c3752 100644 --- a/src/southbridge/intel/i82801dx/Kconfig +++ b/src/southbridge/intel/i82801dx/Kconfig @@ -29,4 +29,8 @@ config EHCI_BAR hex default 0xfef00000 +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/i82801dx/bootblock.c" + endif diff --git a/src/southbridge/intel/i82801dx/bootblock.c b/src/southbridge/intel/i82801dx/bootblock.c new file mode 100644 index 0000000000..8ae419dd9b --- /dev/null +++ b/src/southbridge/intel/i82801dx/bootblock.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +static void bootblock_southbridge_init(void) +{ + /* Set FWH IDs for 2 MB flash part. */ + if (CONFIG_ROM_SIZE == 0x200000) + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111); +} -- cgit v1.2.3