From 3c20cba28930ff86eb65074fc8cb577873901592 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 22 Sep 2019 13:27:20 +0200 Subject: soc/intel/common/smbus: lock TCO base address on PCH finalize MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michael Niewöhner Change-Id: Idab9419487e6e4cbdecd2efaa4772ff4960c9055 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35525 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Marc Jones --- src/soc/intel/common/block/smbus/tco.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src') diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 8cde3bf7f2..518541b1ab 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -24,6 +24,7 @@ #define TCOBASE 0x50 #define TCOCTL 0x54 #define TCO_BASE_EN (1 << 8) +#define TCO_BASE_LOCK (1 << 0) /* Get base address of TCO I/O registers. */ static uint16_t tco_get_bar(void) @@ -52,6 +53,10 @@ void tco_write_reg(uint16_t tco_reg, uint16_t value) void tco_lockdown(void) { uint16_t tcocnt; + const pci_devfn_t dev = PCH_DEV_SMBUS; + + /* TCO base address lockdown */ + pci_or_config32(dev, TCOCTL, TCO_BASE_LOCK); /* TCO Lock down */ tcocnt = tco_read_reg(TCO1_CNT); -- cgit v1.2.3