From 3afa59310308ed1f57ef68c725e01e62fe8ad1ea Mon Sep 17 00:00:00 2001 From: qinwentao Date: Fri, 19 May 2023 15:25:01 +0800 Subject: mb/google/rex/var/screebo: Add BT devicetree config Enabling BT for screebo project BUG=b:278169273 TEST=Check whether BT can connect to Bluetooth device Signed-off-by: qinwentao Change-Id: I0ecd62abfbe751e1036948b1490844e7e63d7f0d Signed-off-by: qinwentao Reviewed-on: https://review.coreboot.org/c/coreboot/+/75352 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Kun Liu Reviewed-by: Eric Lai Reviewed-by: Kapil Porwal --- src/mainboard/google/rex/variants/screebo/overridetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 2e7b208329..ee59f6a342 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -4,6 +4,7 @@ chip soc/intel/meteorlake register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A Port A1 register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 @@ -287,6 +288,12 @@ chip soc/intel/meteorlake register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, CENTER, ACPI_PLD_GROUP(3, 1))" device ref usb2_port9 on end end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)" + device ref usb2_port10 on end + end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" -- cgit v1.2.3