From 38c78889c5dfeda842e3dd8b8698549cd5e71021 Mon Sep 17 00:00:00 2001 From: Rudolf Marek Date: Tue, 12 Nov 2013 16:46:47 +0100 Subject: Asus F2A85-M: Fix S3 memory power cut-off MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The power to memory is lost during the the suspend, activate the 3VSBSW# which switches the power during S3 suspend sequence. As a result resuming from suspend to RAM works now, but now the GPP ports of the Hudson southbridge are gone after resume from S3. The devices 15.0 and 15.1 are disabled (decode as ffff) and therefore anything behind them too [1]. [1] http://www.coreboot.org/pipermail/coreboot/2013-November/076620.html fam15tn hudson PCIe GPP ports off after resume Change-Id: Id953313ee4400a03a2ad8ca09e39a5e0d5f92524 Signed-off-by: Rudolf Marek Reviewed-on: http://review.coreboot.org/4041 Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/asus/f2a85-m/romstage.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 5d01bb44fe..031bb50d5f 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -90,6 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sbxxx_enable_48mhzout(); it8712f_kill_watchdog(); it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + it8712f_enable_3vsbsw(); console_init(); /* turn on secondary smbus at b20 */ -- cgit v1.2.3