From 386b084ee187e7705d16c7f67f28b62d02eb9ca9 Mon Sep 17 00:00:00 2001 From: Chris Wang Date: Thu, 22 Nov 2018 00:03:29 +0800 Subject: mb/google/kahlee: Enable 2T mode for liara in DVT phase Change the board id detection to support rev5, since the 2T mode still needed in DVT build. BUG=b:116082728 TEST=verify by ODM. Change-Id: Ibb4cc1fd2bb54984cb7a8856ed7b9f49b78eddce Signed-off-by: Chris Wang Reviewed-on: https://review.coreboot.org/c/29779 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/kahlee/OemCustomize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 12e50724ec..fc8ff32901 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -58,7 +58,7 @@ static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = { void OemPostParams(AMD_POST_PARAMS *PostParams) { - if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4)) + if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 5)) PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4LiaraMemoryConfiguration; else -- cgit v1.2.3