From 37c33052e5c32cfd732b149ec0748614ce5f0178 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Sat, 2 Apr 2022 10:33:00 +0530 Subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating The patch adds mechanism in the Alder Lake SoC code to control PCH USB2 Phy power gating from brya board variant's devicetree. Please refer Intel doc#723158 for more information. BUG=b:221461379 TEST=Build and boot Gimble board Signed-off-by: Sridhar Siricilla Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63293 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Subrata Banik --- src/soc/intel/alderlake/chip.h | 7 +++++++ src/soc/intel/alderlake/fsp_params.c | 2 ++ 2 files changed, 9 insertions(+) (limited to 'src') diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 2dae9cd202..8ee36f63bc 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -573,6 +573,13 @@ struct soc_intel_alderlake_config { * Default 0. Set this to 1 in order to disable C state demotion. */ bool disable_c1_state_auto_demotion; + + /* + * Enable or Disable PCH USB2 Phy power gating. + * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating. + * Workaround for Intel TA# 723158 to prevent possible display flicker. + */ + bool usb2_phy_sus_pg_disable; }; typedef struct soc_intel_alderlake_config config_t; diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 157bf351df..58f7579f7d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -500,6 +500,8 @@ static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, if (config->tcss_ports[i].enable) s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; } + + s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable; } static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, -- cgit v1.2.3