From 37231fb2feef20b8cc4a7fc039130ed560c93334 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 25 Sep 2021 15:26:12 +0530 Subject: soc/intel/common/../cse: Perform D0I3 bit reset/set prior sending EOP Prior to coreboot sending EOP messages during post, it's important to ensure that CSE is not in Idle state. In case CSE is in Dev Idle state (which means D0I3 bit is set), reset this bit before sending EOP command. This patch ensures coreboot has provision to send CSE EOP messages even after the FSP Notify phase without any delays waiting for the device to respond or timeout. BUG=b:200644229 TEST=Able to send CSE EOP message even after FSP Notify phase. Attempting CSE EOP msg sending post FSP notify without this code change causes `timeout` issue as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 171 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post HECI: timed out reading answer! HECI: Failed to receive! HECI: receive Failed HECI: EOP send/receive fail ERROR: Failed to send EOP to CSE, 2 cse: CSE status registers: HFSTS1: 0x90000255, HFSTS2: 0xf10516 HFSTS3: 0x20 VB2:vb2api_fail() Need recovery, reason: 0x31 / 0xc Saving nvdata board_reset() called! full_reset() called! Attempting CSE EOP msg sending post FSP notify with this code change is `successful` as below: BS: BS_PAYLOAD_LOAD exit times (exec / console): 170 / 0 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot Change-Id: Iae1bc52e94b08f97004424ea0c147d6da8aca6e2 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/57805 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela Reviewed-by: Tim Wawrzynczak --- src/soc/intel/common/block/cse/cse_eop.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src') diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index d8c6430b97..0da49b2b49 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -174,9 +174,13 @@ static void handle_cse_eop_result(enum cse_eop_result result) static void set_cse_end_of_post(void *unused) { + set_cse_device_state(DEV_ACTIVE); + timestamp_add_now(TS_ME_BEFORE_END_OF_POST); handle_cse_eop_result(cse_send_eop()); timestamp_add_now(TS_ME_AFTER_END_OF_POST); + + set_cse_device_state(DEV_IDLE); } /* -- cgit v1.2.3