From 3553a16003255009df6c090e8a4959d0b9fb2864 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 17 May 2023 13:59:26 +0530 Subject: =?UTF-8?q?soc/intel:=C2=A0Extend=20fsp=5Fget=5Fpch=5Freset=5Fstat?= =?UTF-8?q?us()=20to=20all=20FSP=20APIs?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch drops the assert check around `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config to ensure `fsp_get_pch_reset_status()` can be used by all other FSP APIs to know the status of the pending reset. As per recent debug it has been found that, FSP is accumulating all platform resets and executing a single reset from FSP Notify Phase. As coreboot skipped calling into the FSP Notify APIs hence, it might have missed the scope to issue the platform reset. Going forward coreboot needs to implement the corresponding logic to be able to identify any pending platform reset request and execute to complete the silicon initialization flow. BUG=b:282266168 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik Change-Id: I2c9e37fadc27eab820a3121e47e09529de34d10e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75309 Reviewed-by: Sean Rhodes Reviewed-by: Lean Sheng Tan Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/common/fsp_reset.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src') diff --git a/src/soc/intel/common/fsp_reset.c b/src/soc/intel/common/fsp_reset.c index 3a34aaddb5..2bb39bd5a3 100644 --- a/src/soc/intel/common/fsp_reset.c +++ b/src/soc/intel/common/fsp_reset.c @@ -70,8 +70,6 @@ static uint32_t fsp_reset_type_to_status(EFI_RESET_TYPE reset_type) */ uint32_t fsp_get_pch_reset_status(void) { - assert(CONFIG(FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN)); - size_t size; const struct fsp_reset_hob *hob = fsp_find_extension_hob_by_guid(fsp_reset_guid, &size); if (!hob) -- cgit v1.2.3