From 351aff85ee0c694e791ac7647ed9f49d7d9e6e99 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 21 May 2014 15:07:26 -0600 Subject: device/pci_ids.h: defines for new Intel LPC devices MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add defines for the Cave Creek and Rangeley LPC devices. These chipsets will be added shortly. This file is outside of any of the directories that will be touched by those additions, so it's getting changed in its own commit. Change-Id: Ia829282b2ad67eef09689858500bc7f93a1cd05b Signed-off-by: Martin Roth Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/5810 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan Reviewed-by: Kyösti Mälkki --- src/include/device/pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 50ab96caca..4f15c377be 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2531,10 +2531,13 @@ #define PCI_DEVICE_ID_INTEL_82801IO_LPC 0x2914 #define PCI_DEVICE_ID_INTEL_82801IH_LPC 0x2912 +#define PCI_DEVICE_ID_INTEL_CAVECREEK_LPC 0x2310 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f +#define PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MIN 0x1f38 +#define PCI_DEVICE_ID_INTEL_RANGELEY_LPC_MAX 0x1f3b #define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc /* Intel 82801E (C-ICH) */ -- cgit v1.2.3