From 33c0aac3b642b1f2a3cef5d3c32b150148eee90a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 24 Jan 2021 12:56:12 +0100 Subject: soc/intel/*: drop incomplete and unneeded check for DMI SRLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Before enabling IO decode ranges, current code checks if the DMI SRLOCK is set to prevent inconsistencies between LPC PCI cfg registers and LPC DMI registers, when the latter are locked. DMI SRLOCK only applies to PCHs with on-package DMI, but not to PCH-H, PCH-S and others with discrete PCH packages. So this check is at least incomplete. Further, the lock gets applied by FSP and gets reset on a warm reset. Thus, there is no case where the lock would be already set at the places where the DMI registers get written currently. Drop the checks for the reasons mentioned above. Change-Id: I59554ce96bce7f7d1a4ba9b098be9e8466c68eac Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49885 Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/bootblock/pch.c | 16 +--------------- src/soc/intel/cannonlake/bootblock/pch.c | 17 +---------------- src/soc/intel/elkhartlake/bootblock/pch.c | 17 +---------------- src/soc/intel/icelake/bootblock/pch.c | 17 +---------------- src/soc/intel/jasperlake/bootblock/pch.c | 17 +---------------- src/soc/intel/skylake/bootblock/pch.c | 17 +---------------- src/soc/intel/tigerlake/bootblock/pch.c | 17 +---------------- 7 files changed, 7 insertions(+), 111 deletions(-) (limited to 'src') diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 3a92661f08..6905834734 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -96,19 +96,6 @@ static void soc_config_acpibase(void) } } -static int pch_check_decode_enable(void) -{ - const uint32_t dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - - /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ - if (dmi_control & PCR_DMI_DMICTL_SRLOCK) - return -1; - return 0; -} - void pch_early_iorange_init(void) { uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | @@ -119,8 +106,7 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) - lpc_enable_fixed_io_ranges(io_enables); + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a618988116..51f8fb59f6 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -113,20 +113,6 @@ static void soc_config_acpibase(void) } } -static int pch_check_decode_enable(void) -{ - uint32_t dmi_control; - - /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ - dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - if (dmi_control & PCR_DMI_DMICTL_SRLOCK) - return -1; - return 0; -} - void pch_early_iorange_init(void) { uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | @@ -137,8 +123,7 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) - lpc_enable_fixed_io_ranges(io_enables); + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index 288589ae90..04849d4c8c 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -94,20 +94,6 @@ static void soc_config_acpibase(void) } } -static int pch_check_decode_enable(void) -{ - uint32_t dmi_control; - - /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ - dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - if (dmi_control & PCR_DMI_DMICTL_SRLOCK) - return -1; - return 0; -} - void pch_early_iorange_init(void) { uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | @@ -118,8 +104,7 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) - lpc_enable_fixed_io_ranges(io_enables); + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 18e611962b..a4166fcf67 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -93,20 +93,6 @@ static void soc_config_acpibase(void) } } -static int pch_check_decode_enable(void) -{ - uint32_t dmi_control; - - /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ - dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - if (dmi_control & PCR_DMI_DMICTL_SRLOCK) - return -1; - return 0; -} - void pch_early_iorange_init(void) { uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | @@ -117,8 +103,7 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) - lpc_enable_fixed_io_ranges(io_enables); + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index 4dc5b08591..df29cd66f0 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -94,20 +94,6 @@ static void soc_config_acpibase(void) } } -static int pch_check_decode_enable(void) -{ - uint32_t dmi_control; - - /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ - dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - if (dmi_control & PCR_DMI_DMICTL_SRLOCK) - return -1; - return 0; -} - void pch_early_iorange_init(void) { uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | @@ -118,8 +104,7 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) - lpc_enable_fixed_io_ranges(io_enables); + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 9fb2aa1b36..b15bf98fa1 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -98,20 +98,6 @@ static void soc_config_pwrmbase(void) pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0); } -static int pch_check_decode_enable(void) -{ - uint32_t dmi_control; - - /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ - dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - if (dmi_control & PCR_DMI_DMICTL_SRLOCK) - return -1; - return 0; -} - void pch_early_iorange_init(void) { uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | @@ -129,8 +115,7 @@ void pch_early_iorange_init(void) } /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) - lpc_enable_fixed_io_ranges(io_enables); + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 96a4487f26..517ca95ac1 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -99,20 +99,6 @@ static void soc_config_acpibase(void) } } -static int pch_check_decode_enable(void) -{ - uint32_t dmi_control; - - /* - * This cycle decoding is only allowed to set when - * DMICTL.SRLOCK is 0. - */ - dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); - if (dmi_control & PCR_DMI_DMICTL_SRLOCK) - return -1; - return 0; -} - void pch_early_iorange_init(void) { uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | @@ -123,8 +109,7 @@ void pch_early_iorange_init(void) lpc_io_setup_comm_a_b(); /* IO Decode Enable */ - if (pch_check_decode_enable() == 0) - lpc_enable_fixed_io_ranges(io_enables); + lpc_enable_fixed_io_ranges(io_enables); /* Program generic IO Decode Range */ pch_enable_lpc(); -- cgit v1.2.3