From 3280aa7df266c964e1b354b18fcd3134f310b776 Mon Sep 17 00:00:00 2001
From: Xiang Wang <wxjstz@126.com>
Date: Wed, 20 Mar 2019 12:04:43 +0800
Subject: riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths

Change-Id: Iabe390963bcbeb9ec6016faa8312d101431942da
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
---
 src/arch/riscv/include/mcall.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h
index 192d2b4564..d7d67ce33b 100644
--- a/src/arch/riscv/include/mcall.h
+++ b/src/arch/riscv/include/mcall.h
@@ -27,7 +27,7 @@
 #endif
 
 /* We save 37 registers, currently. */
-#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8)
+#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * __SIZEOF_POINTER__)
 
 #ifndef __ASSEMBLER__
 
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