From 31ae314f0fa3c06d8dcc9d830b8844acd2299ed4 Mon Sep 17 00:00:00 2001 From: "henryc.chen" Date: Fri, 31 Jul 2015 17:10:52 +0800 Subject: mediatek/mt8173: Add mt6391 PMIC driver BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I2b9e1fc16183a29ba308313d347f2f0e948e96a7 Signed-off-by: Patrick Georgi Original-Commit-Id: ee56cab3b5c04838af80690c21d3aa160d71501a Original-Change-Id: I2eaa0a406c29b7c9012e3c9860967fc3f27a48a5 Original-Signed-off-by: henryc.chen Original-Reviewed-on: https://chromium-review.googlesource.com/292669 Original-Commit-Ready: Yidi Lin Original-Tested-by: Yidi Lin Original-Reviewed-by: Julius Werner Reviewed-on: https://review.coreboot.org/12608 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/oak/bootblock.c | 5 + src/soc/mediatek/mt8173/Makefile.inc | 2 +- src/soc/mediatek/mt8173/bootblock.c | 4 + src/soc/mediatek/mt8173/include/soc/mt6391.h | 311 +++++++++++++++++++ src/soc/mediatek/mt8173/mt6391.c | 434 +++++++++++++++++++++++++++ 5 files changed, 755 insertions(+), 1 deletion(-) create mode 100644 src/soc/mediatek/mt8173/include/soc/mt6391.h create mode 100644 src/soc/mediatek/mt8173/mt6391.c (limited to 'src') diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index e82ad6ea90..54301e401a 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -18,9 +18,11 @@ */ #include +#include #include #include #include +#include #include #include @@ -49,4 +51,7 @@ void bootblock_mainboard_init(void) i2c_set_gpio_pinmux(); setup_chromeos_gpios(); + + if (board_id() < 4) + mt6391_enable_reset_when_ap_resets(); } diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 3f3fb0b9c0..a18d8a8c60 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -28,7 +28,7 @@ ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_DRIVERS_UART) += uart.c endif -bootblock-y += gpio.c gpio_init.c pmic_wrap.c +bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c ################################################################################ diff --git a/src/soc/mediatek/mt8173/bootblock.c b/src/soc/mediatek/mt8173/bootblock.c index aaa7f61cdb..ef09cae45b 100644 --- a/src/soc/mediatek/mt8173/bootblock.c +++ b/src/soc/mediatek/mt8173/bootblock.c @@ -18,12 +18,16 @@ */ #include +#include #include void bootblock_soc_init(void) { mt_pll_init(); + /* init pmic wrap SPI interface and pmic */ + mt6391_init(); + /* post init pll */ mt_pll_post_init(); } diff --git a/src/soc/mediatek/mt8173/include/soc/mt6391.h b/src/soc/mediatek/mt8173/include/soc/mt6391.h new file mode 100644 index 0000000000..304ef229d0 --- /dev/null +++ b/src/soc/mediatek/mt8173/include/soc/mt6391.h @@ -0,0 +1,311 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_MEDIATEK_MT8173_MT6391_H__ +#define __SOC_MEDIATEK_MT8173_MT6391_H__ + +#include + +/* + * PMIC definition + */ +enum { + PMIC6391_E1_CID_CODE = 0x1091, + PMIC6391_E2_CID_CODE = 0x2091, + PMIC6397_E1_CID_CODE = 0x1097, + PMIC6397_E2_CID_CODE = 0x2097, + PMIC6397_E3_CID_CODE = 0x3097, + PMIC6397_E4_CID_CODE = 0x4097 +}; + +/* + * PMIC Register Index + */ + +/* PCHR Register Definition */ +enum { + PMIC_RG_CHR_CON1 = 0x0002, + PMIC_RG_CHR_CON6 = 0x000C, + PMIC_RG_CHR_CON13 = 0x001A, + PMIC_RG_CHR_CON18 = 0x0024, + PMIC_RG_CHR_CON21 = 0x002A, + PMIC_RG_CHR_CON23 = 0x002E, +}; + +/* TOP Register Definition */ +enum{ + PMIC_RG_CID = 0x0100, + PMIC_RG_TOP_CKPDN = 0x0102, + PMIC_RG_TOP_CKPDN2 = 0x0108, + PMIC_RG_TOP_RST_CON = 0x0114, + PMIC_RG_WRP_CKPDN = 0x011A, + PMIC_RG_TOP_RST_MISC = 0x0126, + PMIC_RG_TOP_CKCON1 = 0x0128, + PMIC_RG_TOP_CKCON2 = 0x012A, + PMIC_RG_TOP_CKTST1 = 0x012C, + PMIC_RG_TOP_CKTST2 = 0x012E, + PMIC_RG_OC_DEG_EN = 0x0130, + PMIC_RG_OC_CTL1 = 0x0134, + PMIC_RG_CHRSTATUS = 0x0144, + PMIC_RG_OCSTATUS0 = 0x0146, + PMIC_RG_OCSTATUS1 = 0x0148, + PMIC_RG_OCSTATUS2 = 0x014A, + PMIC_RG_TOP_CKPDN3 = 0x01CE, + PMIC_RG_TOP_CKCON3 = 0x01D4 +}; + +/* INT Register Definition */ +enum{ + PMIC_RG_INT_CON0 = 0x0178, + PMIC_RG_INT_CON1 = 0x017E, +}; + +/* FQMTR Register Definition */ +enum{ + PMIC_RG_FQMTR_CON0 = 0x0188, + PMIC_RG_FQMTR_CON1 = 0x018A, + PMIC_RG_FQMTR_CON2 = 0x018C +}; + +/* EFUSE Register Definition */ +enum{ + PMIC_RG_EFUSE_DOUT_256_271 = 0x01EE, + PMIC_RG_EFUSE_DOUT_272_287 = 0x01F0, + PMIC_RG_EFUSE_DOUT_288_303 = 0x01F2, + PMIC_RG_EFUSE_DOUT_304_319 = 0x01F4 +}; + +/* BUCK Register Definition */ +enum{ + PMIC_RG_BUCK_CON3 = 0x0206, + PMIC_RG_BUCK_CON8 = 0x0210, + PMIC_RG_VCA15_CON1 = 0x0216, + PMIC_RG_VCA15_CON5 = 0x021E, + PMIC_RG_VCA15_CON7 = 0x0222, + PMIC_RG_VCA15_CON8 = 0x0224, + PMIC_RG_VCA15_CON9 = 0x0226, + PMIC_RG_VCA15_CON10 = 0x0228, + PMIC_RG_VCA15_CON11 = 0x022A, + PMIC_RG_VCA15_CON18 = 0x0238, + PMIC_RG_VSRMCA15_CON5 = 0x0244, + PMIC_RG_VSRMCA15_CON6 = 0x0246, + PMIC_RG_VSRMCA15_CON7 = 0x0248, + PMIC_RG_VSRMCA15_CON8 = 0x024A, + PMIC_RG_VSRMCA15_CON9 = 0x024C, + PMIC_RG_VSRMCA15_CON10 = 0x024E, + PMIC_RG_VSRMCA15_CON11 = 0x0250, + PMIC_RG_VSRMCA15_CON18 = 0x025E, + PMIC_RG_VSRMCA15_CON19 = 0x0260, + PMIC_RG_VSRMCA15_CON20 = 0x0262, + PMIC_RG_VSRMCA15_CON21 = 0x0264, + PMIC_RG_VCORE_CON5 = 0x0270, + PMIC_RG_VCORE_CON6 = 0x0272, + PMIC_RG_VCORE_CON8 = 0x0276, + PMIC_RG_VCORE_CON9 = 0x0278, + PMIC_RG_VCORE_CON10 = 0x027A, + PMIC_RG_VCORE_CON11 = 0x027C, + PMIC_RG_VCORE_CON18 = 0x028A, + PMIC_RG_VGPU_CON1 = 0x028E, + PMIC_RG_VGPU_CON8 = 0x029C, + PMIC_RG_VGPU_CON18 = 0x02B0, + PMIC_RG_VIO18_CON18 = 0x0324, + PMIC_RG_VPCA7_CON5 = 0x0330, + PMIC_RG_VPCA7_CON6 = 0x0332, + PMIC_RG_VPCA7_CON7 = 0x0334, + PMIC_RG_VPCA7_CON8 = 0x0336, + PMIC_RG_VPCA7_CON9 = 0x0338, + PMIC_RG_VPCA7_CON10 = 0x033A, + PMIC_RG_VPCA7_CON11 = 0x033C, + PMIC_RG_VPCA7_CON18 = 0x034A, + PMIC_RG_VSRMCA7_CON5 = 0x0356, + PMIC_RG_VSRMCA7_CON6 = 0x0358, + PMIC_RG_VSRMCA7_CON8 = 0x035C, + PMIC_RG_VSRMCA7_CON9 = 0x035E, + PMIC_RG_VSRMCA7_CON10 = 0x0360, + PMIC_RG_VSRMCA7_CON11 = 0x0362, + PMIC_RG_VSRMCA7_CON18 = 0x0370, + PMIC_RG_VSRMCA7_CON19 = 0x0372, + PMIC_RG_VSRMCA7_CON20 = 0x0374, + PMIC_RG_VSRMCA7_CON21 = 0x0376, + PMIC_RG_VDRM_CON9 = 0x038A, + PMIC_RG_VDRM_CON10 = 0x038C, + PMIC_RG_VDRM_CON18 = 0x039C, + PMIC_RG_BUCK_K_CON0 = 0x039E +}; + +/* ANALDO Register Definition */ +enum{ + PMIC_RG_ANALDO_CON0 = 0x0400, + PMIC_RG_ANALDO_CON2 = 0x0404, + PMIC_RG_ANALDO_CON6 = 0x040C, +}; + +/* DIGLDO Register Definition */ +enum{ + PMIC_RG_DIGLDO_CON5 = 0x041A, + PMIC_RG_DIGLDO_CON6 = 0x041C, + PMIC_RG_DIGLDO_CON8 = 0x0420, + PMIC_RG_DIGLDO_CON10 = 0x0424, + PMIC_RG_DIGLDO_CON19 = 0x0436, + PMIC_RG_DIGLDO_CON20 = 0x0438, + PMIC_RG_DIGLDO_CON22 = 0x043C, + PMIC_RG_DIGLDO_CON24 = 0x0440, + PMIC_RG_DIGLDO_CON27 = 0x0446, + PMIC_RG_DIGLDO_CON30 = 0x044C, + PMIC_RG_DIGLDO_CON33 = 0x045A +}; + +/* STRUP Register Definition */ +enum{ + PMIC_RG_STRUP_CON0 = 0x0500, + PMIC_RG_STRUP_CON2 = 0x0502, + PMIC_RG_STRUP_CON5 = 0x0508, + PMIC_RG_STRUP_CON7 = 0x050C, + PMIC_RG_STRUP_CON10 = 0x0512 +}; + +/* AUXADC Register Definition */ +enum{ + PMIC_RG_AUXADC_CON14 = 0x055E +}; + +/* Driver Register Definition */ +enum{ + PMIC_RG_FLASH_CON0 = 0x0560, + PMIC_RG_KPLED_CON0 = 0x0566 +}; + +/* SPK Register Definition */ +enum{ + PMIC_RG_SPK_CON0 = 0x0600, + PMIC_RG_SPK_CON2 = 0x0604, + PMIC_RG_SPK_CON3 = 0x0606, + PMIC_RG_SPK_CON5 = 0x060A, + PMIC_RG_SPK_CON9 = 0x0612 +}; + +/* FGADC Register Definition */ +enum{ + PMIC_RG_FGADC_CON13 = 0x0632, + PMIC_RG_FGADC_CON16 = 0x0638, + PMIC_RG_FGADC_CON17 = 0x063A, + PMIC_RG_FGADC_CON18 = 0x063C +}; + +/* AUDDAC Register Definition */ +enum{ + PMIC_RG_AUDLDO_CFG0 = 0x0714, + PMIC_RG_AUD_NCP0 = 0x071A +}; + +/* DCXO Register Definition */ +enum{ + PMIC_RG_PMIC_RG_RG_DCXO_CON0 = 0x83a, + PMIC_RG_DCXO_CON2 = 0x83e, + PMIC_RG_DCXO_MANUAL_CON1 = 0x844, + PMIC_RG_DCXO_ANALOG_CON1 = 0x84a, + PMIC_RG_DCXO_FORCE_MODE1 = 0x854, + PMIC_RG_DCXO_POR2_CON3 = 0x85c +}; + +/* TOP MASK and SHIFT Definition */ +enum{ + PMIC_RG_FQMTR_PDN_SHIFT = 1, + PMIC_RG_AP_RST_DIS_MASK = 0x1, + PMIC_RG_AP_RST_DIS_SHIFT = 0, + PMIC_RG_RST_PART_SEL_MASK = 0x1, + PMIC_RG_RST_PART_SEL_SHIFT = 4, + PMIC_RG_TOP_RST_MISC_RSV_3_MASK = 0x1, + PMIC_RG_TOP_RST_MISC_RSV_3_SHIFT = 3, + PMIC_RG_STRUP_MAN_RST_EN_MASK = 0x1, + PMIC_RG_STRUP_MAN_RST_EN_SHIFT = 2, + PMIC_RG_SYSRSTB_EN_MASK = 0x1, + PMIC_RG_SYSRSTB_EN_SHIFT = 1, + PMIC_RG_PWRKEY_DEB_MASK = 0x1, + PMIC_RG_PWRKEY_DEB_SHIFT = 3, + PMIC_RG_HOMEKEY_DEB_MASK = 0x1, + PMIC_RG_HOMEKEY_DEB_SHIFT = 4 +}; + +/* ANALDO MASK and SHIFT Definition */ +enum{ + PMIC_RG_VCAMA_VOSEL_MASK = 0x3, + PMIC_RG_VCAMA_VOSEL_SHIFT = 6, + PMIC_RG_VCAMA_EN_MASK = 0x1, + PMIC_RG_VCAMA_EN_SHIFT = 15, +}; + +/* DCXO MASK and SHIFT Definition */ +enum{ + PMIC_RG_DCXO_C2_UNTRIM_MASK = 0x1, + PMIC_RG_DCXO_C2_UNTRIM_SHIFT = 15, + PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_MASK = 0x1, + PMIC_RG_DCXO_MANUAL_C1C2_SYNC_EN_SHIFT = 9, + PMIC_RG_DCXO_MANUAL_SYNC_EN_MASK = 0x1, + PMIC_RG_DCXO_MANUAL_SYNC_EN_SHIFT = 8, + PMIC_RG_DCXO_ATTEN_BB_MASK = 0x3, + PMIC_RG_DCXO_ATTEN_BB_SHIFT = 11, + PMIC_RG_DCXO_LDO_BB_V_MASK = 0x3, + PMIC_RG_DCXO_LDO_BB_V_SHIFT = 2 +}; + +enum ldo_power { + LDO_VCAMD, + LDO_VCAMIO, + LDO_VCAMAF, + LDO_VGP4, + LDO_VGP5, + LDO_VGP6, + LDO_VTCXO, + LDO_VA28, + LDO_VCAMA, + LDO_VIO28, + LDO_VUSB, + LDO_VMC, + LDO_VMCH, + LDO_VEMC3V3, + LDO_VIBR, +}; + +enum ldo_voltage { + LDO_1P2 = 0, + LDO_1P3 = 1, + LDO_1P5 = 2, + LDO_1P8 = 3, + LDO_2P5 = 4, + LDO_2P8 = 5, + LDO_3P0 = 6, + LDO_3P3 = 7, + LDO_NUM_VOLTAGES, + + LDO_1P22, /* only VCAMD */ + LDO_1P0, /* only VCAMIO */ + LDO_2P0, /* only VGP5 */ +}; + +/* + * PMIC Exported Function + */ +void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel); +u32 mt6391_read(u16 reg, u32 mask, u32 shift); +void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift); +void mt6391_enable_reset_when_ap_resets(void); +void mt6391_init(void); + +#endif /* __SOC_MEDIATEK_MT8173_MT6391_H__ */ diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c new file mode 100644 index 0000000000..49fc0b0a4d --- /dev/null +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -0,0 +1,434 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include + +#if CONFIG_DEBUG_PMIC +#define DEBUG_PMIC(level, x...) printk(level, x) +#else +#define DEBUG_PMIC(level, x...) +#endif + +u32 mt6391_read(u16 reg, u32 mask, u32 shift) +{ + u16 rdata; + + pwrap_wacs2(0, reg, 0, &rdata, 1); + rdata &= (mask << shift); + rdata = (rdata >> shift); + + DEBUG_PMIC(BIOS_INFO, "[%s] Reg[%#x]=%#x\n", + __func__, reg, rdata); + return rdata; +} + +void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift) +{ + u16 rdata; + u16 old_rdata, new_rdata; + + pwrap_wacs2(0, reg, 0, &rdata, 1); + old_rdata = rdata; + + rdata &= ~(mask << shift); + rdata |= (val << shift); + new_rdata = rdata; + + pwrap_wacs2(1, reg, rdata, &rdata, 1); + + DEBUG_PMIC(BIOS_INFO, "[%s] write Reg[%#x]=%#x -> %#x\n", + __func__, reg, old_rdata, new_rdata); + return; +} + +void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel) +{ + u16 addr; + switch (ldo) { + case LDO_VCAMD: + assert(vsel != 0); + if (vsel == LDO_1P22) + vsel = 0; + break; + case LDO_VCAMIO: + assert(vsel != 1); + if (vsel == LDO_1P0) + vsel = 1; + break; + case LDO_VGP5: + assert(vsel != 7); + if (vsel == LDO_2P0) + vsel = 7; + break; + default: + break; + } + assert(vsel < LDO_NUM_VOLTAGES); + + if (ldo == LDO_VGP6) + addr = PMIC_RG_DIGLDO_CON33; + else + addr = PMIC_RG_DIGLDO_CON19 + ldo * 2; + + mt6391_write(addr, vsel, 0x7, 5); + mt6391_write(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15); + +} + +void mt6391_enable_reset_when_ap_resets(void) +{ + /* Enable AP watchdog reset */ + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 0); +} + +static void mt6391_init_setting(void) +{ + /* Enable PMIC RST function (depends on main chip RST function) */ + /* + * state1: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=1, RG_RST_PART_SEL=1 + * state2: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=0, RG_RST_PART_SEL=1 + * state3: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=x, RG_RST_PART_SEL=0 + */ + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 1); + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 2); + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 4); + + /* Disable AP watchdog reset */ + mt6391_write(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 0); + + /* Enable CA15 by default for different PMIC behavior */ + mt6391_write(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0); + mt6391_write(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0); + mt6391_write(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0); + udelay(200); /* delay for Buck ready */ + + /* [3:3]: RG_PWMOC_CK_PDN; For OC protection */ + mt6391_write(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3); + /* [9:9]: RG_SRCVOLT_HW_AUTO_EN; */ + mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 9); + /* [8:8]: RG_OSC_SEL_AUTO; */ + mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 8); + /* [6:6]: RG_SMPS_DIV2_SRC_AUTOFF_DIS; */ + mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 6); + /* [5:5]: RG_SMPS_AUTOFF_DIS; */ + mt6391_write(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 5); + /* [7:7]: VDRM_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 7); + /* [6:6]: VSRMCA7_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 6); + /* [5:5]: VPCA7_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 5); + /* [4:4]: VIO18_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 4); + /* [3:3]: VGPU_DEG_EN; For OC protection */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 3); + /* [2:2]: VCORE_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 2); + /* [1:1]: VSRMCA15_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 1); + /* [0:0]: VCA15_DEG_EN; */ + mt6391_write(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 0); + /* [11:11]: RG_INT_EN_THR_H; */ + mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 11); + /* [10:10]: RG_INT_EN_THR_L; */ + mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 10); + /* [4:4]: RG_INT_EN_BAT_L; */ + mt6391_write(PMIC_RG_INT_CON0, 0x1, 0x1, 4); + /* [11:11]: RG_INT_EN_VGPU; OC protection */ + mt6391_write(PMIC_RG_INT_CON1, 0x1, 0x1, 11); + /* [8:8]: RG_INT_EN_VCA15; OC protection */ + mt6391_write(PMIC_RG_INT_CON1, 0x1, 0x1, 8); + /* [12:0]: BUCK_RSV; for OC protection */ + mt6391_write(PMIC_RG_BUCK_CON3, 0x600, 0x0FFF, 0); + /* [11:10]: QI_VCORE_VSLEEP; sleep mode only (0.7V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 10); + /* [7:6]: QI_VSRMCA7_VSLEEP; sleep mode only (0.85V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 6); + /* [5:4]: QI_VSRMCA15_VSLEEP; sleep mode only (0.7V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 4); + /* [3:2]: QI_VPCA7_VSLEEP; sleep mode only (0.85V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x0, 0x3, 2); + /* [1:0]: QI_VCA15_VSLEEP; sleep mode only (0.7V) */ + mt6391_write(PMIC_RG_BUCK_CON8, 0x1, 0x3, 0); + /* [13:12]: RG_VCA15_CSL2; for OC protection */ + mt6391_write(PMIC_RG_VCA15_CON1, 0x0, 0x3, 12); + /* [11:10]: RG_VCA15_CSL1; for OC protection */ + mt6391_write(PMIC_RG_VCA15_CON1, 0x0, 0x3, 10); + /* [15:15]: VCA15_SFCHG_REN; soft change rising enable */ + mt6391_write(PMIC_RG_VCA15_CON8, 0x1, 0x1, 15); + /* [14:8]: VCA15_SFCHG_RRATE; soft change rising step=0.5 */ + mt6391_write(PMIC_RG_VCA15_CON8, 0x5, 0x7F, 8); + /* [7:7]: VCA15_SFCHG_FEN; soft change falling enable */ + mt6391_write(PMIC_RG_VCA15_CON8, 0x1, 0x1, 7); + /* [6:0]: VCA15_SFCHG_FRATE; soft change falling step=2us */ + mt6391_write(PMIC_RG_VCA15_CON8, 0x17, 0x7F, 0); + /* [6:0]: VCA15_VOSEL_SLEEP; sleep mode only (0.7V) */ + mt6391_write(PMIC_RG_VCA15_CON11, 0x0, 0x7F, 0); + /* [8:8]: VCA15_VSLEEP_EN; set sleep mode reference volt */ + mt6391_write(PMIC_RG_VCA15_CON18, 0x1, 0x1, 8); + /* [5:4]: VCA15_VOSEL_TRANS_EN; rising & falling enable */ + mt6391_write(PMIC_RG_VCA15_CON18, 0x3, 0x3, 4); + /* [5:5]: VSRMCA15_TRACK_SLEEP_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 5); + /* [5:4]: VSRMCA15_VOSEL_SEL; */ + mt6391_write(PMIC_RG_VSRMCA15_CON6, 0x0, 0x3, 4); + /* [15:15]: VSRMCA15_SFCHG_REN; */ + mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 15); + /* [14:8]: VSRMCA15_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x5, 0x7F, 8); + /* [7:7]: VSRMCA15_SFCHG_FEN; */ + mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 7); + /* [6:0]: VSRMCA15_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0); + /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */ + mt6391_write(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0); + /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode referenc */ + mt6391_write(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8); + /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */ + mt6391_write(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4); + /* [1:1]: VCORE_VOSEL_CTRL; sleep mode voltage control fo */ + mt6391_write(PMIC_RG_VCORE_CON5, 0x1, 0x1, 1); + /* [5:4]: VCORE_VOSEL_SEL; */ + mt6391_write(PMIC_RG_VCORE_CON6, 0x0, 0x3, 4); + /* [15:15]: VCORE_SFCHG_REN; */ + mt6391_write(PMIC_RG_VCORE_CON8, 0x1, 0x1, 15); + /* [14:8]: VCORE_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VCORE_CON8, 0x5, 0x7F, 8); + /* [6:0]: VCORE_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VCORE_CON8, 0x17, 0x7F, 0); + /* [6:0]: VCORE_VOSEL_SLEEP; Sleep mode setting only (0. */ + mt6391_write(PMIC_RG_VCORE_CON11, 0x0, 0x7F, 0); + /* [8:8]: VCORE_VSLEEP_EN; Sleep mode HW control R2R to */ + mt6391_write(PMIC_RG_VCORE_CON18, 0x1, 0x1, 8); + /* [5:4]: VCORE_VOSEL_TRANS_EN; Follows MT6320 VCORE set */ + mt6391_write(PMIC_RG_VCORE_CON18, 0x0, 0x3, 4); + /* [1:0]: VCORE_TRANSTD; */ + mt6391_write(PMIC_RG_VCORE_CON18, 0x3, 0x3, 0); + /* [9:8]: RG_VGPU_CSL; for OC protection */ + mt6391_write(PMIC_RG_VGPU_CON1, 0x1, 0x3, 8); + /* [15:15]: VGPU_SFCHG_REN; */ + mt6391_write(PMIC_RG_VGPU_CON8, 0x1, 0x1, 15); + /* [14:8]: VGPU_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VGPU_CON8, 0x5, 0x7F, 8); + /* [6:0]: VGPU_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VGPU_CON8, 0x17, 0x7F, 0); + /* [5:4]: VGPU_VOSEL_TRANS_EN; */ + mt6391_write(PMIC_RG_VGPU_CON18, 0x0, 0x3, 4); + /* [1:0]: VGPU_TRANSTD; */ + mt6391_write(PMIC_RG_VGPU_CON18, 0x3, 0x3, 0); + /* [5:4]: VPCA7_VOSEL_SEL; */ + mt6391_write(PMIC_RG_VPCA7_CON6, 0x0, 0x3, 4); + /* [15:15]: VPCA7_SFCHG_REN; */ + mt6391_write(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 15); + /* [14:8]: VPCA7_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VPCA7_CON8, 0x5, 0x7F, 8); + /* [7:7]: VPCA7_SFCHG_FEN; */ + mt6391_write(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 7); + /* [6:0]: VPCA7_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VPCA7_CON8, 0x17, 0x7F, 0); + /* [6:0]: VPCA7_VOSEL_SLEEP; */ + mt6391_write(PMIC_RG_VPCA7_CON11, 0x18, 0x7F, 0); + /* [8:8]: VPCA7_VSLEEP_EN; */ + mt6391_write(PMIC_RG_VPCA7_CON18, 0x0, 0x1, 8); + /* [5:4]: VPCA7_VOSEL_TRANS_EN; */ + mt6391_write(PMIC_RG_VPCA7_CON18, 0x3, 0x3, 4); + /* [5:5]: VSRMCA7_TRACK_SLEEP_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 5); + /* [5:4]: VSRMCA7_VOSEL_SEL; */ + mt6391_write(PMIC_RG_VSRMCA7_CON6, 0x0, 0x3, 4); + /* [15:15]: VSRMCA7_SFCHG_REN; */ + mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 15); + /* [14:8]: VSRMCA7_SFCHG_RRATE; */ + mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x5, 0x7F, 8); + /* [7:7]: VSRMCA7_SFCHG_FEN; */ + mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 7); + /* [6:0]: VSRMCA7_SFCHG_FRATE; */ + mt6391_write(PMIC_RG_VSRMCA7_CON8, 0x17, 0x7F, 0); + /* [6:0]: VSRMCA7_VOSEL_SLEEP; */ + mt6391_write(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0); + /* [8:8]: VSRMCA7_VSLEEP_EN; */ + mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x1, 0x1, 8); + /* [5:4]: VSRMCA7_VOSEL_TRANS_EN; */ + mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4); + /* [8:8]: VDRM_VSLEEP_EN; */ + mt6391_write(PMIC_RG_VDRM_CON18, 0x1, 0x1, 8); + /* [2:2]: VIBR_THER_SHEN_EN; */ + mt6391_write(PMIC_RG_DIGLDO_CON24, 0x1, 0x1, 2); + /* [5:5]: THR_HWPDN_EN; */ + mt6391_write(PMIC_RG_STRUP_CON0, 0x1, 0x1, 5); + /* [3:3]: RG_RST_DRVSEL; */ + mt6391_write(PMIC_RG_STRUP_CON2, 0x1, 0x1, 3); + /* [2:2]: RG_EN_DRVSEL; */ + mt6391_write(PMIC_RG_STRUP_CON2, 0x1, 0x1, 2); + /* [1:1]: PWRBB_DEB_EN; */ + mt6391_write(PMIC_RG_STRUP_CON5, 0x1, 0x1, 1); + /* [12:12]: VSRMCA15_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 12); + /* [11:11]: VPCA15_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 11); + /* [10:10]: VCORE_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 10); + /* [9:9]: VSRMCA7_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 9); + /* [8:8]: VPCA7_PG_H2L_EN; */ + mt6391_write(PMIC_RG_STRUP_CON7, 0x1, 0x1, 8); + /* [1:1]: STRUP_PWROFF_PREOFF_EN; */ + mt6391_write(PMIC_RG_STRUP_CON10, 0x1, 0x1, 1); + /* [0:0]: STRUP_PWROFF_SEQ_EN; */ + mt6391_write(PMIC_RG_STRUP_CON10, 0x1, 0x1, 0); + /* [15:8]: RG_ADC_TRIM_CH_SEL; */ + mt6391_write(PMIC_RG_AUXADC_CON14, 0xFC, 0xFF, 8); + /* [1:1]: FLASH_THER_SHDN_EN; */ + mt6391_write(PMIC_RG_FLASH_CON0, 0x1, 0x1, 1); + /* [1:1]: KPLED_THER_SHDN_EN; */ + mt6391_write(PMIC_RG_KPLED_CON0, 0x1, 0x1, 1); + /* [14:8]: VSRMCA15_VOSEL_OFFSET; set offset=100mV */ + mt6391_write(PMIC_RG_VSRMCA15_CON19, 0x10, 0x7F, 8); + /* [6:0]: VSRMCA15_VOSEL_DELTA; set delta=0mV */ + mt6391_write(PMIC_RG_VSRMCA15_CON19, 0x0, 0x7F, 0); + /* [14:8]: VSRMCA15_VOSEL_ON_HB; set HB=1.15V */ + mt6391_write(PMIC_RG_VSRMCA15_CON20, 0x48, 0x7F, 8); + /* [6:0]: VSRMCA15_VOSEL_ON_LB; set LB=0.7V */ + mt6391_write(PMIC_RG_VSRMCA15_CON20, 0x0, 0x7F, 0); + /* [6:0]: VSRMCA15_VOSEL_SLEEP_LB; set sleep LB=0.7V */ + mt6391_write(PMIC_RG_VSRMCA15_CON21, 0x0, 0x7F, 0); + /* [14:8]: VSRMCA7_VOSEL_OFFSET; set offset=25mV */ + mt6391_write(PMIC_RG_VSRMCA7_CON19, 0x4, 0x7F, 8); + /* [6:0]: VSRMCA7_VOSEL_DELTA; set delta=0mV */ + mt6391_write(PMIC_RG_VSRMCA7_CON19, 0x0, 0x7F, 0); + /* [14:8]: VSRMCA7_VOSEL_ON_HB; set HB=1.275V */ + mt6391_write(PMIC_RG_VSRMCA7_CON20, 0x5C, 0x7F, 8); + /* [6:0]: VSRMCA7_VOSEL_ON_LB; set LB=1.05000V */ + mt6391_write(PMIC_RG_VSRMCA7_CON20, 0x38, 0x7F, 0); + /* [6:0]: VSRMCA7_VOSEL_SLEEP_LB; set sleep LB=0.85000 */ + mt6391_write(PMIC_RG_VSRMCA7_CON21, 0x18, 0x7F, 0); + /* [1:1]: VCA15_VOSEL_CTRL, VCA15_EN_CTRL; DVS HW control */ + mt6391_write(PMIC_RG_VCA15_CON5, 0x3, 0x3, 0); + /* [1:1]: VSRMCA15_VOSEL_CTRL, VSRAM15_EN_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x3, 0x3, 0); + /* [1:1]: VPCA7_VOSEL_CTRL; */ + mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1); + /* [1:1]: VSRMCA7_VOSEL_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1); + /* [4:4]: VCA15_TRACK_ON_CTRL; DVFS tracking enable */ + mt6391_write(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4); + /* [4:4]: VSRMCA15_TRACK_ON_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 4); + /* [4:4]: VPCA7_TRACK_ON_CTRL; */ + mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 4); + /* [4:4]: VSRMCA7_TRACK_ON_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 4); + /* [15:14]: VGPU OC; */ + mt6391_write(PMIC_RG_OC_CTL1, 0x3, 0x3, 14); + /* [3:2]: VCA15 OC; */ + mt6391_write(PMIC_RG_OC_CTL1, 0x3, 0x3, 2); + + /* Set VPCA7 to 1.2V */ + mt6391_write(PMIC_RG_VPCA7_CON9, 0x50, 0x7f, 0x0); + mt6391_write(PMIC_RG_VPCA7_CON10, 0x50, 0x7f, 0x0); + /* Set VSRMCA7 to 1.1V */ + mt6391_write(PMIC_RG_VSRMCA7_CON9, 0x40, 0x7f, 0x0); + mt6391_write(PMIC_RG_VSRMCA7_CON10, 0x40, 0x7f, 0x0); + + /* Enable VGP6 and set to 3.3V*/ + mt6391_write(PMIC_RG_DIGLDO_CON10, 0x1, 0x1, 15); + mt6391_write(PMIC_RG_DIGLDO_CON33, 0x07, 0x07, 5); + + /* Set VDRM to 1.21875V */ + mt6391_write(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0); + mt6391_write(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0); + + /* 26M clock amplitute adjust */ + mt6391_write(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2); + mt6391_write(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11); + + /* For low power, set VTCXO switch by SRCVOLTEN */ + mt6391_write(PMIC_RG_DIGLDO_CON27, 0x0100, 0x0100, 0); + /* [6:5]=0(VTCXO_SRCLK_MODE_SEL) */ + mt6391_write(PMIC_RG_ANALDO_CON0, 0, 0x3, 13); + /* [11]=0(VTCXO_ON_CTRL), */ + mt6391_write(PMIC_RG_ANALDO_CON0, 1, 0x1, 11); + /* [10]=1(RG_VTCXO_EN), */ + mt6391_write(PMIC_RG_ANALDO_CON0, 1, 0x1, 10); + /* [4:3]=1(RG_VTCXOTD_SEL) */ + mt6391_write(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3); + /* For low power, VIO18 set sleep_en to HW mode */ + mt6391_write(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8); + +} + +static void mt6391_default_buck_voltage(void) +{ + u16 reg_val = 0; + u16 buck_val = 0; + /* There are two kinds of PMIC used for MT8173 : MT6397s/MT6391. + * MT6397s: the default voltage of register was not suitable for + * MT8173, needs to apply the setting of eFuse. + * VPCA15/VSRMCA15/: 1.15V + * VCORE: 1.05V + * + * MT6391: the default voltage of register was matched for MT8173. + * VPAC15/VCORE/VGPU: 1.0V + * VSRMCA15: 1.0125V + */ + reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_288_303, 0xFFFF, 0); + + if ((reg_val & 0x01) == 0x01) { + /* VCORE */ + reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_256_271, 0xF, 12); + buck_val = mt6391_read(PMIC_RG_VCORE_CON9, 0x7f, 0x0); + + /* VCORE_VOSEL[3:6] => eFuse bit 268-271 */ + buck_val = (buck_val & 0x07) | (reg_val << 3); + mt6391_write(PMIC_RG_VCORE_CON9, buck_val, 0x7f, 0x0); + mt6391_write(PMIC_RG_VCORE_CON10, buck_val, 0x7f, 0x0); + + reg_val = mt6391_read(PMIC_RG_EFUSE_DOUT_272_287, 0xFFFF, 0); + /* VCA15 */ + buck_val = 0; + buck_val = mt6391_read(PMIC_RG_VCA15_CON9, 0x7f, 0x0); + buck_val = (buck_val & 0x07) | ((reg_val & 0x0F) << 3); + mt6391_write(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0); + mt6391_write(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0); + + /* VSAMRCA15 */ + buck_val = 0; + buck_val = mt6391_read(PMIC_RG_VSRMCA15_CON9, 0x7f, 0x0); + buck_val = (buck_val & 0x07) | ((reg_val & 0xF0) >> 1); + mt6391_write(PMIC_RG_VSRMCA15_CON9, buck_val, 0x7f, 0x0); + mt6391_write(PMIC_RG_VSRMCA15_CON10, buck_val, 0x7f, 0x0); + + /* set the power control by register(use original) */ + mt6391_write(PMIC_RG_BUCK_CON3, 0x1, 0x1, 12); + } +} + +void mt6391_init(void) +{ + if (pwrap_init()) + die("ERROR - Failed to initial pmic wrap!"); + /* pmic initial setting */ + mt6391_init_setting(); + + /* Adjust default BUCK voltage from eFuse */ + mt6391_default_buck_voltage(); +} -- cgit v1.2.3