From 314e551447f408300e56cd6206af3e52d9b22059 Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <stepan@coresystems.de>
Date: Fri, 9 Apr 2010 20:36:29 +0000
Subject: This patch changes C7 CAR code to be a single assembler file instead
of the ugly mixture it was before. It also enables CAR for all C7 boards
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
src/arch/i386/Makefile.inc | 10 +--
src/cpu/Kconfig | 2 +-
src/cpu/via/car/cache_as_ram.inc | 136 ++++++++++++++++++++++++++++---
src/cpu/via/car/cache_as_ram.lds | 30 -------
src/cpu/via/car/cache_as_ram_post.c | 109 -------------------------
src/cpu/via/model_c7/Kconfig | 13 +++
src/mainboard/bcom/winnetp680/romstage.c | 2 +-
src/mainboard/jetway/j7f24/Kconfig | 10 ---
src/mainboard/jetway/j7f24/romstage.c | 2 +-
src/mainboard/via/epia-cn/Kconfig | 11 ---
src/mainboard/via/epia-cn/romstage.c | 2 +-
src/mainboard/via/epia-m700/Kconfig | 11 ---
src/mainboard/via/epia-m700/romstage.c | 105 +-----------------------
src/mainboard/via/pc2500e/Kconfig | 11 ---
src/mainboard/via/pc2500e/romstage.c | 2 +-
src/mainboard/via/vt8454c/Kconfig | 11 ---
src/mainboard/via/vt8454c/romstage.c | 16 +---
17 files changed, 146 insertions(+), 337 deletions(-)
delete mode 100644 src/cpu/via/car/cache_as_ram.lds
delete mode 100644 src/cpu/via/car/cache_as_ram_post.c
(limited to 'src')
diff --git a/src/arch/i386/Makefile.inc b/src/arch/i386/Makefile.inc
index a403b9bab7..adc2d92aca 100644
--- a/src/arch/i386/Makefile.inc
+++ b/src/arch/i386/Makefile.inc
@@ -37,7 +37,7 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL) $(call
ifeq ($(CONFIG_PAYLOAD_NONE),y)
printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n"
else
- printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n"
+ printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n"
$(CBFSTOOL) $@.tmp add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
endif
ifeq ($(CONFIG_VGA_BIOS),y)
@@ -165,11 +165,7 @@ endif
ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCBGA479),y)
crt0s += $(src)/cpu/x86/car/cache_as_ram.inc
endif
-# should be CONFIG_CPU_VIA_C7, but bcom/winnetp680, jetway/j7f24, via/epia-cn, via/pc2500e don't use CAR yet
-ifeq ($(CONFIG_BOARD_VIA_VT8454C),y)
-crt0s += $(src)/cpu/via/car/cache_as_ram.inc
-endif
-ifeq ($(CONFIG_BOARD_VIA_EPIA_M700),y)
+ifeq ($(CONFIG_CPU_VIA_C7),y)
crt0s += $(src)/cpu/via/car/cache_as_ram.inc
endif
# who else could use this?
@@ -208,7 +204,7 @@ endif
ifeq ($(CONFIG_ROMCC),y)
ROMCCFLAGS ?= -mcpu=p2 -O2
-$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h
+$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h
printf " ROMCC romstage.inc\n"
$(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $< -o $@
else
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index c63cf2b52d..1b72f6e5aa 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -5,7 +5,7 @@ source src/cpu/x86/Kconfig
config USE_DCACHE_RAM
bool
- default n
+ default !ROMCC
config DCACHE_RAM_BASE
hex
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index ba0fadfec5..7eb85333ac 100644
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -63,6 +63,20 @@ clear_fixed_var_mtrr:
wrmsr
jmp clear_fixed_var_mtrr
+
+fixed_mtrr_msr:
+ .long 0x250, 0x258, 0x259
+ .long 0x268, 0x269, 0x26A
+ .long 0x26B, 0x26C, 0x26D
+ .long 0x26E, 0x26F
+
+var_mtrr_msr:
+ .long 0x200, 0x201, 0x202, 0x203
+ .long 0x204, 0x205, 0x206, 0x207
+ .long 0x208, 0x209, 0x20A, 0x20B
+ .long 0x20C, 0x20D, 0x20E, 0x20F
+ .long 0x000 /* NULL, end of table */
+
clear_fixed_var_mtrr_out:
/* MTRRPhysBase */
movl $0x200, %ecx
@@ -163,17 +177,113 @@ testok: movb $0x40,%al
/* We need to set ebp ? No need */
movl %esp, %ebp
pushl %eax /* bist */
- call stage1_main
- /* We will not go back */
+ call main
+
+ /*
+ * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
+ * get STACK up, we restore that. It is only needed if we
+ * want to go back.
+ */
+
+ /* We don't need cache as ram for now on */
+ /* disable cache */
+ movl %cr0, %eax
+ orl $(0x1<<30),%eax
+ movl %eax, %cr0
+
+
+ /* Set the default memory type and disable fixed and enable variable MTRRs */
+ movl $0x2ff, %ecx
+ //movl $MTRRdefType_MSR, %ecx
+ xorl %edx, %edx
+
+ /* Enable Variable and Disable Fixed MTRRs */
+ movl $0x00000800, %eax
+ wrmsr
+
+ /* enable caching for first 1M using variable mtrr */
+ movl $0x200, %ecx
+ xorl %edx, %edx
+ movl $(0 | 6), %eax
+ //movl $(0 | MTRR_TYPE_WRBACK), %eax
+ wrmsr
+
+ /* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
+ * If 1M cacheable, then when S3 resume, there is stange color on
+ * screen for 2 sec. suppose problem of a0000-dfffff and cache.
+ * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
+ */
+
+ movl $0x201, %ecx
+ movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
+ movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
+ wrmsr
+
+ movl $0x202, %ecx
+ xorl %edx, %edx
+ movl $(0x80000 | 6), %eax
+ orl $(0 | 6), %eax
+ wrmsr
+
+ movl $0x203, %ecx
+ movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
+ movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
+ wrmsr
+
+ movl $0x204, %ecx
+ xorl %edx, %edx
+ movl $(0xc0000 | 6), %eax
+ orl $(0 | 6), %eax
+ wrmsr
+
+ movl $0x205, %ecx
+ movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
+ movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
+ wrmsr
+
+ /* cache CONFIG_XIP_ROM_BASE-SIZE to speedup coreboot code */
+ movl $0x206, %ecx
+ xorl %edx, %edx
+ movl $CONFIG_XIP_ROM_BASE,%eax
+ orl $(0 | 6), %eax
+ wrmsr
+
+ movl $0x207, %ecx
+ xorl %edx, %edx
+ movl $CONFIG_XIP_ROM_SIZE,%eax
+ decl %eax
+ notl %eax
+ orl $(0 | 0x800), %eax
+ wrmsr
+
+ /* enable cache */
+ movl %cr0, %eax
+ andl $0x9fffffff,%eax
+ movl %eax, %cr0
+ invd
+
+ /* clear boot_complete flag */
+ xorl %ebp, %ebp
+__main:
+ post_code(0x11)
+ cld /* clear direction flag */
+
+ movl %ebp, %esi
+
+ /* FIXME: These values might have to change for suspend-to-ram.
+ * the 0x00400000 was chosen as this is a place in memory that
+ * should exist in all contemporary configurations (ie. large
+ * enough RAM), but doesn't collide with anything coreboot does.
+ * Other than that, it's arbitrary.
+ */
+
+ movl $0x4000000, %esp
+ movl %esp, %ebp
+ pushl %esi
+ call copy_and_run
+
+.Lhlt:
+ post_code(0xee)
+ hlt
+ jmp .Lhlt
-fixed_mtrr_msr:
- .long 0x250, 0x258, 0x259
- .long 0x268, 0x269, 0x26A
- .long 0x26B, 0x26C, 0x26D
- .long 0x26E, 0x26F
-var_mtrr_msr:
- .long 0x200, 0x201, 0x202, 0x203
- .long 0x204, 0x205, 0x206, 0x207
- .long 0x208, 0x209, 0x20A, 0x20B
- .long 0x20C, 0x20D, 0x20E, 0x20F
- .long 0x000 /* NULL, end of table */
diff --git a/src/cpu/via/car/cache_as_ram.lds b/src/cpu/via/car/cache_as_ram.lds
deleted file mode 100644
index fc9b11291e..0000000000
--- a/src/cpu/via/car/cache_as_ram.lds
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Carl-Daniel Hailfinger
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-SECTIONS {
- .init . : {
- _init = .;
- *(.init.text);
- *(.init.rodata);
- *(.init.rodata.*);
- . = ALIGN(16);
- _einit = .;
- }
-}
diff --git a/src/cpu/via/car/cache_as_ram_post.c b/src/cpu/via/car/cache_as_ram_post.c
deleted file mode 100644
index 3c5c5e486b..0000000000
--- a/src/cpu/via/car/cache_as_ram_post.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
- __asm__ volatile (
- /*
- FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
- It is only needed if we want to go back
- */
-
- /* We don't need cache as ram for now on */
- /* disable cache */
- "movl %cr0, %eax\n\t"
- "orl $(0x1<<30),%eax\n\t"
- "movl %eax, %cr0\n\t"
-
-
- /* Set the default memory type and disable fixed and enable variable MTRRs */
- "movl $0x2ff, %ecx\n\t"
- //"movl $MTRRdefType_MSR, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- /* Enable Variable and Disable Fixed MTRRs */
- "movl $0x00000800, %eax\n\t"
- "wrmsr\n\t"
-
- /* enable caching for first 1M using variable mtrr */
- "movl $0x200, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- "movl $(0 | 6), %eax\n\t"
- //"movl $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
- "wrmsr\n\t"
-
-/*Jasonzhao@viatech.com.cn, I enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
-if 1M cacheable,then when S3 resume, there is stange color on screen for 2 sec.
-suppose problem of a0000-dfffff and cache .
-and in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.*/
-
- "movl $0x201, %ecx\n\t"
- "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
- "movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax\n\t"
- "wrmsr\n\t"
-
- "movl $0x202, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- "movl $(0x80000 | 6), %eax\n\t"
- "orl $(0 | 6), %eax\n\t"
- "wrmsr\n\t"
-
- "movl $0x203, %ecx\n\t"
- "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
- "movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax\n\t"
- "wrmsr\n\t"
-
- "movl $0x204, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- "movl $(0xc0000 | 6), %eax\n\t"
- "orl $(0 | 6), %eax\n\t"
- "wrmsr\n\t"
-
- "movl $0x205, %ecx\n\t"
- "movl $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
- "movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax\n\t"
- "wrmsr\n\t"
-
- /*jasonzhao@viatech.com.cn add this 2008-11-27, cache CONFIG_XIP_ROM_BASE-SIZE to speedup the coreboot code*/
- "movl $0x206, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- "movl $CONFIG_XIP_ROM_BASE,%eax\n\t"
- "orl $(0 | 6), %eax\n\t"
- "wrmsr\n\t"
-
- "movl $0x207, %ecx\n\t"
- "xorl %edx, %edx\n\t"
- "movl $CONFIG_XIP_ROM_SIZE,%eax\n\t"
- "decl %eax\n\t"
- "notl %eax\n\t"
- "orl $(0 | 0x800), %eax\n\t"
- "wrmsr\n\t"
-
- /* enable cache */
- "movl %cr0, %eax\n\t"
- "andl $0x9fffffff,%eax\n\t"
- "movl %eax, %cr0\n\t"
- "invd\n\t"
-
- /* FIXME: These values might have to change for suspend-to-ram.
- the 0x00400000 was chosen as this is a place in memory that
- should exist in all contemporary configurations (ie. large
- enough RAM), but doesn't collide with anything coreboot does.
- Other than that, it's arbitrary. */
- "movl $0x00400000,%esp\n\t"
- "movl %esp,%ebp\n\t"
- );
diff --git a/src/cpu/via/model_c7/Kconfig b/src/cpu/via/model_c7/Kconfig
index 530898cf6e..7790b95ee8 100644
--- a/src/cpu/via/model_c7/Kconfig
+++ b/src/cpu/via/model_c7/Kconfig
@@ -3,3 +3,16 @@ config CPU_VIA_C7
select UDELAY_TSC
select MMX
select SSE2
+ select USE_PRINTK_IN_CAR
+
+config DCACHE_RAM_BASE
+ hex
+ default 0xffef0000
+ depends on CPU_VIA_C7
+
+config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+ depends on CPU_VIA_C7
+
+
diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c
index f1511574d4..4bd7a45844 100644
--- a/src/mainboard/bcom/winnetp680/romstage.c
+++ b/src/mainboard/bcom/winnetp680/romstage.c
@@ -87,7 +87,7 @@ static const struct mem_controller ctrl = {
.channel0 = { 0x50 },
};
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
unsigned long x;
device_t dev;
diff --git a/src/mainboard/jetway/j7f24/Kconfig b/src/mainboard/jetway/j7f24/Kconfig
index 6890f1a45e..e1afc27e8a 100644
--- a/src/mainboard/jetway/j7f24/Kconfig
+++ b/src/mainboard/jetway/j7f24/Kconfig
@@ -14,16 +14,6 @@ config MAINBOARD_DIR
default jetway/j7f24
depends on BOARD_JETWAY_J7F24
-#config DCACHE_RAM_BASE
-# hex
-# default 0xffef0000
-# depends on BOARD_JETWAY_J7F24
-#
-#config DCACHE_RAM_SIZE
-# hex
-# default 0x8000
-# depends on BOARD_JETWAY_J7F24
-
config MAINBOARD_PART_NUMBER
string
default "J7f24"
diff --git a/src/mainboard/jetway/j7f24/romstage.c b/src/mainboard/jetway/j7f24/romstage.c
index 67eda8e8b5..3903684945 100644
--- a/src/mainboard/jetway/j7f24/romstage.c
+++ b/src/mainboard/jetway/j7f24/romstage.c
@@ -87,7 +87,7 @@ static const struct mem_controller ctrl = {
.channel0 = { 0x50 },
};
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
diff --git a/src/mainboard/via/epia-cn/Kconfig b/src/mainboard/via/epia-cn/Kconfig
index be824330d9..4e50133e5e 100644
--- a/src/mainboard/via/epia-cn/Kconfig
+++ b/src/mainboard/via/epia-cn/Kconfig
@@ -5,7 +5,6 @@ config BOARD_VIA_EPIA_CN
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_VIA_VT1211
- select ROMCC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_512
@@ -14,16 +13,6 @@ config MAINBOARD_DIR
default via/epia-cn
depends on BOARD_VIA_EPIA_CN
-#config DCACHE_RAM_BASE
-# hex
-# default 0xffef0000
-# depends on BOARD_VIA_EPIA_CN
-#
-#config DCACHE_RAM_SIZE
-# hex
-# default 0x8000
-# depends on BOARD_VIA_EPIA_CN
-
config MAINBOARD_PART_NUMBER
string
default "EPIA-CN"
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index c68c753dad..5fbf84337e 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -86,7 +86,7 @@ static const struct mem_controller ctrl = {
.channel0 = { 0x50 },
};
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
unsigned long x;
device_t dev;
diff --git a/src/mainboard/via/epia-m700/Kconfig b/src/mainboard/via/epia-m700/Kconfig
index fe3b799eb3..91bb11ccc5 100644
--- a/src/mainboard/via/epia-m700/Kconfig
+++ b/src/mainboard/via/epia-m700/Kconfig
@@ -7,23 +7,12 @@ config BOARD_VIA_EPIA_M700
select BOARD_HAS_FADT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
- select USE_PRINTK_IN_CAR
config MAINBOARD_DIR
string
default via/epia-m700
depends on BOARD_VIA_EPIA_M700
-config DCACHE_RAM_BASE
- hex
- default 0xffef0000
- depends on BOARD_VIA_EPIA_M700
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
- depends on BOARD_VIA_EPIA_M700
-
config MAINBOARD_PART_NUMBER
string
default "EPIA-M700"
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index d10e5d16cf..6f8a1c09da 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -381,7 +381,7 @@ void EmbedComInit(void)
}
/* cache_as_ram.inc jumps to here. */
-void stage1_main(unsigned long bist)
+void main(unsigned long bist)
{
unsigned cpu_reset = 0;
u16 boot_mode;
@@ -686,108 +686,5 @@ void stage1_main(unsigned long bist)
#endif
-/*
- * The following code is copied from tyan\s2735\romstage.c.
- * Only the code around CLEAR_FIRST_1M_RAM is changed. Removed all the code
- * around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c".
- * The CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop
- * at somewhere, and cpu/x86/car/cache_as_ram_post.c do not cache my
- * $CONFIG_XIP_ROM_BASE+SIZE area.
- *
- * Use #include "cpu/via/car/cache_as_ram_post.c". This version post.c have
- * some diff with x86-version.
- */
-#if 1
- {
- /*
- * Check value of esp to verify if we have enough ROM for
- * stack in Cache as RAM.
- */
- unsigned v_esp;
- __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp));
-#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp);
-#else
- print_debug("v_esp=");
- print_debug_hex32(v_esp);
- print_debug("\n");
-#endif
- }
-#endif
-
-#if 1
-cpu_reset_x:
-
- /* It seems that cpu_reset is not used before this, so I just reset
- * it, (this is because the s3 resume, setting in MTRR and copy data
- * may destroy stack.
- */
- cpu_reset = 0;
-
-#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset);
-#else
- print_debug("cpu_reset = ");
- print_debug_hex32(cpu_reset);
- print_debug("\n");
-#endif
-
- if (cpu_reset == 0)
- print_debug("Clearing initial memory region: ");
- print_debug("No cache as ram now - ");
-
- /* Store cpu_reset to ebx. */
- __asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset));
-
- /*
- * Cancel these lines, CLEAR_FIRST_1M_RAM cause the
- * cpu/x86/car/cache_as_ram_post.c stop at somewhere.
- */
-#if 0
- if (cpu_reset == 0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cpu/via/car/cache_as_ram_post.c"
- } else {
-#undef CLEAR_FIRST_1M_RAM
-#include "cpu/via/car/cache_as_ram_post.c"
- }
-#endif
-
-#include "cpu/via/car/cache_as_ram_post.c"
-/* #include "cpu/x86/car/cache_as_ram_post.c" */
- __asm__ volatile (
- /* Set new esp *//* before CONFIG_RAMBASE */
- "subl %0, %%ebp\n\t"
- "subl %0, %%esp\n\t"::
- "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_RAMBASE)
- );
-
- {
- unsigned new_cpu_reset;
-
- /* Get back cpu_reset from ebx. */
- __asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset));
-
- /* We can't go back anymore, we lost old stack data in CAR. */
- if (new_cpu_reset == 0)
- print_debug("Use Ram as Stack now - done\n");
- else
- print_debug("Use Ram as Stack now - \n");
-
-#if CONFIG_USE_PRINTK_IN_CAR
- printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset);
-#else
- print_debug("new_cpu_reset = ");
- print_debug_hex32(new_cpu_reset);
- print_debug("\n");
-#endif
-
- /* Copy and execute coreboot_ram. */
- copy_and_run(new_cpu_reset);
- /* We will not return. */
- }
-#endif
-
- print_debug("should not be here -\n");
}
diff --git a/src/mainboard/via/pc2500e/Kconfig b/src/mainboard/via/pc2500e/Kconfig
index 90afe97bf1..a23ec454cd 100644
--- a/src/mainboard/via/pc2500e/Kconfig
+++ b/src/mainboard/via/pc2500e/Kconfig
@@ -5,7 +5,6 @@ config BOARD_VIA_PC2500E
select NORTHBRIDGE_VIA_CN700
select SOUTHBRIDGE_VIA_VT8237R
select SUPERIO_ITE_IT8716F
- select ROMCC
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select SMP
@@ -22,16 +21,6 @@ config MAINBOARD_PART_NUMBER
default "pc2500e"
depends on BOARD_VIA_PC2500E
-config DCACHE_RAM_BASE
- hex
- default 0xc0000
- depends on BOARD_VIA_PC2500E
-
-config DCACHE_RAM_SIZE
- hex
- default 0x1000
- depends on BOARD_VIA_PC2500E
-
config RAMBASE
hex
default 0x4000
diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c
index 71ad25908a..c0b34ab153 100644
--- a/src/mainboard/via/pc2500e/romstage.c
+++ b/src/mainboard/via/pc2500e/romstage.c
@@ -58,7 +58,7 @@ static const struct mem_controller ctrl = {
.channel0 = { 0x50 }, /* TODO: CN700 currently only supports 1 DIMM. */
};
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
diff --git a/src/mainboard/via/vt8454c/Kconfig b/src/mainboard/via/vt8454c/Kconfig
index eec8195fb1..f575e8098f 100644
--- a/src/mainboard/via/vt8454c/Kconfig
+++ b/src/mainboard/via/vt8454c/Kconfig
@@ -8,7 +8,6 @@ config BOARD_VIA_VT8454C
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
# select MMCONF_SUPPORT
- select USE_PRINTK_IN_CAR
select HAVE_HARD_RESET
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_512
@@ -19,16 +18,6 @@ config MAINBOARD_DIR
default via/vt8454c
depends on BOARD_VIA_VT8454C
-config DCACHE_RAM_BASE
- hex
- default 0xffef0000
- depends on BOARD_VIA_VT8454C
-
-config DCACHE_RAM_SIZE
- hex
- default 0x8000
- depends on BOARD_VIA_VT8454C
-
config MAINBOARD_PART_NUMBER
string
default "VT8454c"
diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c
index f7815bb305..dea85bc234 100644
--- a/src/mainboard/via/vt8454c/romstage.c
+++ b/src/mainboard/via/vt8454c/romstage.c
@@ -32,8 +32,6 @@
#include "northbridge/via/cx700/raminit.h"
#include "cpu/x86/bist.h"
-#define DEACTIVATE_CAR 1
-#define DEACTIVATE_CAR_FILE "cpu/via/car/cache_as_ram_post.c"
#include "pc80/udelay_io.c"
#include "lib/delay.c"
@@ -89,7 +87,7 @@ static void enable_shadow_ram(const struct mem_controller *ctrl)
pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg);
}
-static void main(unsigned long bist)
+void main(unsigned long bist)
{
/* Set statically so it should work with cx700 as well */
static const struct mem_controller cx700[] = {
@@ -115,17 +113,5 @@ static void main(unsigned long bist)
sdram_set_registers(cx700);
enable_shadow_ram(cx700);
sdram_enable(cx700);
-
-#ifdef DEACTIVATE_CAR
- print_debug("Deactivating CAR");
-#include DEACTIVATE_CAR_FILE
- print_debug(" - Done.\n");
-#endif
- copy_and_run(0);
-}
-
-void stage1_main(unsigned long bist)
-{
- main(bist);
}
--
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