From 31324c64e12135f09590884421cbcbcabec1a62f Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <stefan.reinauer@coreboot.org>
Date: Thu, 5 Apr 2012 21:22:02 +0200
Subject: Fill out ChromeOS specific coreboot table extensions

ChromeOS uses two extensions to the coreboot table:
- ChromeOS specific GPIO description for onboard switches
- position of verified boot area in nvram

Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/866
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
---
 src/arch/x86/boot/coreboot_table.c          | 43 +++++++++++++++++++++++++++++
 src/arch/x86/include/arch/coreboot_tables.h |  2 ++
 src/include/boot/coreboot_tables.h          | 36 ++++++++++++++++++++++++
 3 files changed, 81 insertions(+)

(limited to 'src')

diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index a9ff6f0f1b..219de7adae 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -179,6 +179,39 @@ static void lb_framebuffer(struct lb_header *header)
 #endif
 }
 
+#if CONFIG_CHROMEOS
+static void lb_gpios(struct lb_header *header)
+{
+	struct lb_gpios *gpios;
+	gpios = (struct lb_gpios *)lb_new_record(header);
+	gpios->tag = LB_TAG_GPIO;
+	gpios->size = sizeof(*gpios);
+	gpios->count = 0;
+	fill_lb_gpios(gpios);
+}
+
+static void lb_vdat(struct lb_header *header)
+{
+	struct lb_vdat* vdat;
+
+	vdat = (struct lb_vdat *)lb_new_record(header);
+	vdat->tag = LB_TAG_VDAT;
+	vdat->size = sizeof(*vdat);
+	acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size);
+}
+
+static void lb_vbnv(struct lb_header *header)
+{
+	struct lb_vbnv* vbnv;
+
+	vbnv = (struct lb_vbnv *)lb_new_record(header);
+	vbnv->tag = LB_TAG_VBNV;
+	vbnv->size = sizeof(*vbnv);
+	vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14;
+	vbnv->vbnv_size = CONFIG_VBNV_SIZE;
+}
+#endif
+
 static void add_cbmem_pointers(struct lb_header *header)
 {
 	/*
@@ -654,6 +687,16 @@ unsigned long write_coreboot_table(
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+#if CONFIG_CHROMEOS
+	/* Record our GPIO settings (ChromeOS specific) */
+	lb_gpios(head);
+
+	/* pass along the VDAT buffer adress */
+	lb_vdat(head);
+
+	/* pass along VBNV offsets in CMOS */
+	lb_vbnv(head);
+#endif
 	add_cbmem_pointers(head);
 
 	/* Remember where my valid memory ranges are */
diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h
index 773e053835..b177949fb1 100644
--- a/src/arch/x86/include/arch/coreboot_tables.h
+++ b/src/arch/x86/include/arch/coreboot_tables.h
@@ -20,4 +20,6 @@ struct lb_memory *get_lb_mem(void);
 int add_mainboard_resources(struct lb_memory *mem);
 int add_northbridge_resources(struct lb_memory *mem);
 
+void fill_lb_gpios(struct lb_gpios *gpios);
+
 #endif /* COREBOOT_TABLE_H */
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 5535a38a7c..5d5ca2cf56 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -195,6 +195,33 @@ struct lb_framebuffer {
 	uint8_t reserved_mask_size;
 };
 
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_VDAT	0x0015
+struct lb_vdat {
+	uint32_t tag;
+	uint32_t size;
+
+	void	*vdat_addr;
+	uint32_t vdat_size;
+};
+
 #define LB_TAG_TIMESTAMPS	0x0016
 #define LB_TAG_CBMEM_CONSOLE	0x0017
 #define LB_TAG_MRC_CACHE	0x0018
@@ -205,6 +232,15 @@ struct lb_cbmem_ref {
 	void	*cbmem_addr;
 };
 
+#define LB_TAG_VBNV		0x0019
+struct lb_vbnv {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t vbnv_start;
+	uint32_t vbnv_size;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */
-- 
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