From 2f72a204a79729d77308ae12c0e9eaf0c329f366 Mon Sep 17 00:00:00 2001 From: Peichao Wang Date: Tue, 31 Dec 2019 11:24:13 +0800 Subject: mb/google/kahlee/treeya: tune eDP delay time to 20 ms tune eDP delay time to 20 ms ensure satisfy panel spec BUG=b:147270512 TEST=verify panel sequences by ODM. Signed-off-by: Peichao Wang Change-Id: Ia38fbcb976de55baae480d33c6000c91dc9de6bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38024 Reviewed-by: Martin Roth Reviewed-by: chris wang Tested-by: build bot (Jenkins) --- src/mainboard/google/kahlee/variants/treeya/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index e35f00c380..019dcf65ed 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -23,6 +23,8 @@ chip soc/amd/stoneyridge register "stapm_percent" = "68" register "stapm_time_ms" = "900000" register "stapm_power_mw" = "7800" + register "lvds_poseq_varybl_to_blon" = "0x5" + register "lvds_poseq_blon_to_varybl" = "0x5" # Enable I2C0 for audio, USB3 hub at 400kHz register "i2c[0]" = "{ -- cgit v1.2.3