From 2f2ceef27b6b4f8c9adc8110e73cb4aa6618134a Mon Sep 17 00:00:00 2001 From: Roger Wang Date: Wed, 22 May 2024 14:18:33 +0800 Subject: mb/google/nissa/var/sundance: Update eMMC DLL settings Currently Samsung eMMC (KLMBG2JETD-B041) can't power on to OS nomally. According to Intel provides eMMC DLL delay patch that tuning on each Sundance different eMMC system to modify some system can't boot to OS problem. BUG=b:342057438 TEST=Build and check each SKU eMMC can work. Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Signed-off-by: Roger Wang Reviewed-on: https://review.coreboot.org/c/coreboot/+/82602 Reviewed-by: Paul Menzel Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- .../google/brya/variants/sundance/overridetree.cb | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb index 2f944d47fc..b4c7b5ebbc 100644 --- a/src/mainboard/google/brya/variants/sundance/overridetree.cb +++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb @@ -9,6 +9,51 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39, total 625ps. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39, total 625ps. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78, total 465ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79, total 465ps. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79, total 3500ps. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 5250ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79, total 5000ps. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79, total 5000ps. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119, total 3500ps. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 3375ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119, total 3250ps. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119, total 3375ps. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1A1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39, total 0ps. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79, total 5000ps. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps. + # [6:0] Rx Strobe Delay DLL 2 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + # SOC Aux orientation override: # This is a bitfield that corresponds to up to 4 TCSS ports. # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. -- cgit v1.2.3