From 2ed80b16b3099c827bb76baa1976625d4b574e24 Mon Sep 17 00:00:00 2001 From: Ashish Kumar Mishra Date: Thu, 28 Mar 2024 14:49:32 +0530 Subject: mb/google/brox: Enable SAGv Enable SaGv support for brox BUG=None BRANCH=None TEST=Boot brox with SAGv enabled and verify in fsp debug logs Change-Id: I80c44e7df1d75732c6982b27e44ecd6060b1b3f1 Signed-off-by: Ashish Kumar Mishra Reviewed-on: https://review.coreboot.org/c/coreboot/+/81556 Reviewed-by: Krishna P Bhat D Reviewed-by: Shelley Chen Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 9ed0602e2e..f901db9735 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -11,6 +11,9 @@ chip soc/intel/alderlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Enable SAGv + register "sagv" = "SaGv_Enabled" + # S0ix enable register "s0ix_enable" = "1" -- cgit v1.2.3