From 2cc5f550c72ac6a13da798b8f073e3d5c55177e0 Mon Sep 17 00:00:00 2001 From: Scott Duplichan Date: Sun, 15 May 2011 21:54:04 +0000 Subject: Enable SPI cacheline prefetch early to reduce boot time. Signed-off-by: Scott Duplichan Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6584 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/persimmon/romstage.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src') diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index e3ed847fdb..da2db64071 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -50,6 +50,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr (0xc0010062, 0); + // early enable of PrefetchEnSPIFromHost + if (boot_cpu()) + { + __outdword (0xcf8, 0x8000a3b8); + __outdword (0xcfc, __indword (0xcfc) | 0 << 24); + } + // early enable of SPI 33 MHz fast mode read if (boot_cpu()) { -- cgit v1.2.3