From 2b4da16ea410c7536ec7cb9f600877ec5ae8e502 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 5 Apr 2021 19:16:16 +0200 Subject: mb/hp/280_g2/romstage.c: Correct CaVrefConfig setting With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1. Change-Id: I64606824b4f82affb0fcfc78e68ba29859a1cc69 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/52110 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/hp/280_g2/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/hp/280_g2/romstage.c b/src/mainboard/hp/280_g2/romstage.c index 8f32d2495a..9b3d385b42 100644 --- a/src/mainboard/hp/280_g2/romstage.c +++ b/src/mainboard/hp/280_g2/romstage.c @@ -23,8 +23,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) get_spd_smbus(&blk); + mem_cfg->CaVrefConfig = 2; mem_cfg->DqPinsInterleaved = true; - mem_cfg->UserBd = BOARD_TYPE_DESKTOP; mem_cfg->MemorySpdDataLen = blk.len; -- cgit v1.2.3