From 29a52c8308ab270c46c1d859db308ba1de5d1e81 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 13 Oct 2020 23:32:55 +0200 Subject: soc/intel/broadwell: Add ECC config reporting This has been taken from Haswell, and is just to reduce differences. Change-Id: Ib872cbcd20d6e212b1f55400aa350dc6ba44dc2a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46367 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/soc/intel/broadwell/romstage/raminit.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 65e386a7c7..7020ddfe0d 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -21,6 +21,13 @@ #include #include +static const char *const ecc_decoder[] = { + "inactive", + "active on IO", + "disabled on IO", + "active", +}; + /* * Dump in the log memory controller configuration as read from the memory * controller registers. @@ -43,7 +50,7 @@ static void report_memory_config(void) const u32 ch_conf = MCHBAR32(MAD_DIMM(i)); printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); - + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); -- cgit v1.2.3