From 27ce8e3296fb6a55c286b7ff84a03102e41d7a3a Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Wed, 12 Aug 2020 09:50:48 +0200
Subject: sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'

Change-Id: I1a70eea8c4f835e5673e75282c9cecb24b150e3d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
---
 src/southbridge/intel/lynxpoint/early_pch.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index e74fdc5849..85f9f33a97 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -6,6 +6,7 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/smbus_host.h>
+#include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/pmclib.h>
 #include <elog.h>
 #include "pch.h"
@@ -57,7 +58,7 @@ static void pch_generic_setup(void)
 {
 	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
 	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
-	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
+	write_pmbase16(0x60 | 0x08, (1 << 11));	/* halt timer */
 	printk(BIOS_DEBUG, " done.\n");
 }
 
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