From 26ad42572862ca7dbcc541c60d579e14d69a0980 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 4 Apr 2023 13:35:38 +0200 Subject: mb/siemens/mc_ehl4: Change NC FPGA PCIe RP connection for POST codes Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to '0'. On this mainboard NC FPGA is connected to PCIe root port #1 (00:1c.0). Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig index ee725cc71b..21789d7b8e 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl4/Kconfig @@ -22,7 +22,7 @@ config EARLY_PCI_BRIDGE_DEVICE config EARLY_PCI_BRIDGE_FUNCTION hex depends on NC_FPGA_POST_CODE - default 0x2 + default 0x0 config EARLY_PCI_MMIO_BASE hex -- cgit v1.2.3