From 25387927c052aadd07746723e6cff10ab2b40d29 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 10 Jan 2022 09:15:56 +0000 Subject: soc/intel/common/gpio: Add PCH `Pad Configuration Lock` options This patch provides the possible options for PCH to allow `Pad Configuration Lock`. `SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI` config is for Tiger Lake Point (TGP) and Alder Lake Point (ADP) PCH. BUG=b:211573253, b:211950520 TEST=None Signed-off-by: Subrata Banik Change-Id: I7cf35893ab613b154a1073060081a09e561ffe56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60964 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela Reviewed-by: Nick Vaccaro --- src/soc/intel/common/block/gpio/Kconfig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src') diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index c946545355..03a3b092c0 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -36,4 +36,19 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT bool default n +config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI + bool + default n + help + From TGL PCH onwards,`Pad Configuration Lock` can only be set or cleared + using non-posted sideband write. + +config SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR + bool + default n + depends on !SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI + help + SoC user to select this config if `Pad Configuration Lock` can only be set or + cleared using private configuration register (PCR) write. + endif -- cgit v1.2.3