From 24a65f8019e7b9b000bc8b7eb2947a07e6424293 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Thu, 23 Apr 2020 14:04:38 +0900 Subject: mb/google/nightfury: Tune the usb2_port[0] strength Update usb2 port strength parameter for usb2_port[0] to improve SI. BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports Signed-off-by: Seunghwan Kim Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/variants/nightfury/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb index 4b985d933e..2c759bc4bb 100644 --- a/src/mainboard/google/hatch/variants/nightfury/overridetree.cb +++ b/src/mainboard/google/hatch/variants/nightfury/overridetree.cb @@ -23,7 +23,7 @@ chip soc/intel/cannonlake # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" -- cgit v1.2.3