From 242f1d962f24193499795106466923e1f78a4485 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 6 Jun 2021 16:58:19 +0300 Subject: cpu/x86/lapic: Do not inline some utility functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit They are not __always_inline and specially enable_lapic() will become more complex to support X2APIC state changes. Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/55258 Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans Reviewed-by: Wonkyu Kim Tested-by: build bot (Jenkins) --- src/cpu/x86/lapic/Makefile.inc | 7 ++++++- src/cpu/x86/lapic/lapic.c | 37 ++++++++++++++++++++++++++++++++++++- src/include/cpu/x86/lapic.h | 37 +++---------------------------------- 3 files changed, 45 insertions(+), 36 deletions(-) (limited to 'src') diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index ea160148cf..8e89d29f68 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,4 +1,3 @@ -ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-$(CONFIG_SMP) += secondary.S bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c @@ -10,3 +9,9 @@ verstage_x86-y += boot_cpu.c romstage-y += boot_cpu.c ramstage-y += boot_cpu.c postcar-y += boot_cpu.c + +bootblock-y += lapic.c +verstage_x86-y += lapic.c +romstage-y += lapic.c +ramstage-y += lapic.c +postcar-y += lapic.c diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 468a5dc256..9f3cff5834 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -1,10 +1,37 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include #include -void lapic_virtual_wire_mode_init(void) +void enable_lapic(void) +{ + msr_t msr; + msr = rdmsr(LAPIC_BASE_MSR); + msr.hi &= 0xffffff00; + msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; + msr.lo |= LAPIC_DEFAULT_BASE; + msr.lo |= LAPIC_BASE_MSR_ENABLE; + wrmsr(LAPIC_BASE_MSR, msr); +} + +void disable_lapic(void) +{ + msr_t msr; + msr = rdmsr(LAPIC_BASE_MSR); + msr.lo &= ~LAPIC_BASE_MSR_ENABLE; + wrmsr(LAPIC_BASE_MSR, msr); +} + +/* See if I need to initialize the local APIC */ +static int need_lapic_init(void) +{ + return CONFIG(SMP) || CONFIG(IOAPIC); +} + +static void lapic_virtual_wire_mode_init(void) { /* this is so interrupts work. This is very limited scope -- * linux will do better later, we hope ... @@ -40,3 +67,11 @@ void lapic_virtual_wire_mode_init(void) printk(BIOS_DEBUG, " apic_id: 0x%x ", lapicid()); printk(BIOS_INFO, "done.\n"); } + +void setup_lapic(void) +{ + if (need_lapic_init()) + lapic_virtual_wire_mode_init(); + else + disable_lapic(); +} diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index cf048a883e..a3d0fcbf89 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -116,25 +116,6 @@ static __always_inline void lapic_wait_icr_idle(void) do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY); } -static inline void enable_lapic(void) -{ - msr_t msr; - msr = rdmsr(LAPIC_BASE_MSR); - msr.hi &= 0xffffff00; - msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK; - msr.lo |= LAPIC_DEFAULT_BASE; - msr.lo |= LAPIC_BASE_MSR_ENABLE; - wrmsr(LAPIC_BASE_MSR, msr); -} - -static inline void disable_lapic(void) -{ - msr_t msr; - msr = rdmsr(LAPIC_BASE_MSR); - msr.lo &= ~LAPIC_BASE_MSR_ENABLE; - wrmsr(LAPIC_BASE_MSR, msr); -} - static __always_inline unsigned int initial_lapicid(void) { uint32_t lapicid; @@ -168,20 +149,8 @@ static __always_inline void stop_this_cpu(void) void stop_this_cpu(void); #endif -void lapic_virtual_wire_mode_init(void); - -/* See if I need to initialize the local APIC */ -static inline int need_lapic_init(void) -{ - return CONFIG(SMP) || CONFIG(IOAPIC); -} - -static inline void setup_lapic(void) -{ - if (need_lapic_init()) - lapic_virtual_wire_mode_init(); - else - disable_lapic(); -} +void enable_lapic(void); +void disable_lapic(void); +void setup_lapic(void); #endif /* CPU_X86_LAPIC_H */ -- cgit v1.2.3