From 230639b620d8ccc34771e7a1c2ff4b748cf89868 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Wed, 7 Nov 2018 12:36:32 -0800 Subject: mb/google/poppy/variant/nocturne: configure SAR irqs to use PLTRST GPIO's that use GPI_APIC setting with DEEP causes an IRQ storm after S3 resume. GPIOs that fire IRQs via IOAPIC need to get their logic reset over PLTRST to prevent IRQ storm after S3 resume and hence configuring GPP_D9 and GPP_D10 to use PLTRST. BUG=b:119202293 TEST=none Change-Id: I98d71100f28fb9bae05db3fb7d9afcb3f81beb43 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/29538 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/poppy/variants/nocturne/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/poppy/variants/nocturne/gpio.c b/src/mainboard/google/poppy/variants/nocturne/gpio.c index 9aa7706df4..70b748b045 100644 --- a/src/mainboard/google/poppy/variants/nocturne/gpio.c +++ b/src/mainboard/google/poppy/variants/nocturne/gpio.c @@ -180,9 +180,9 @@ static const struct pad_config gpio_table[] = { /* D8 : ISH_I2C1_SCL ==> NC */ PAD_CFG_NC(GPP_D8), /* D9 : ISH_SPI_CS# ==> PCH_SR1_INT_L */ - PAD_CFG_GPI_APIC(GPP_D9, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_D9, NONE, PLTRST), /* D10 : ISH_SPI_CLK ==> PCH_SR0_INT_L */ - PAD_CFG_GPI_APIC(GPP_D10, NONE, DEEP), + PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST), /* D11 : ISH_SPI_MISO ==> NC */ PAD_CFG_NC(GPP_D11), /* D12 : ISH_SPI_MOSI ==> NC */ -- cgit v1.2.3