From 21b303dc54329c910a20d4a61ece7225a20815e4 Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Mon, 6 Jul 2020 21:44:54 +0530 Subject: mb/intel/jasperlake_rvp: Skip CPU Replacement Check for jasperlake rvp This patch enables the SkipCpuReplacementCheck config for jasperlake rvp to avoid the forced MRC training with the soldered down SOC. BUG=b:160201335 BRANCH=None TEST=Build and verify on jasperlake rvp with CSE Lite SKU. Cq-Depend: chrome-internal:3142530 Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/43146 Reviewed-by: Karthik Ramasubramanian Reviewed-by: Sridhar Siricilla Reviewed-by: Rizwan Qureshi Tested-by: build bot (Jenkins) --- src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 14ca4a5abd..616e35c1b4 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -55,6 +55,9 @@ chip soc/intel/jasperlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" + # Skip the CPU repalcement check + register "SkipCpuReplacementCheck" = "1" + register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" register "PchHdaAudioLinkSspEnable[0]" = "1" -- cgit v1.2.3