From 20b261dacf56a0bf09a74931cd511537b79b6983 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 20 Jan 2009 21:32:37 +0000 Subject: Fix register typo for core 2 cpus (trivial) This bug was reported a long time ago by Thomas Jourdan. Thanks a lot Thomas. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/model_6fx/cache_as_ram.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/cpu/intel/model_6fx/cache_as_ram.inc b/src/cpu/intel/model_6fx/cache_as_ram.inc index 2395f4d4fc..d04274046d 100644 --- a/src/cpu/intel/model_6fx/cache_as_ram.inc +++ b/src/cpu/intel/model_6fx/cache_as_ram.inc @@ -39,7 +39,7 @@ cache_as_ram: movl %eax, (%esi) /* Disable prefetchers */ - movl $0x01a0, %eax + movl $0x01a0, %ecx rdmsr orl $((1 << 9) | (1 << 19)), %eax orl $((1 << 5) | (1 << 7)), %edx -- cgit v1.2.3