From 200d213d1bae614fcd35913c1d46fec7e495717f Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Fri, 6 Dec 2019 12:07:52 +0100 Subject: amdblocks/pci: add common implementation of MMCONF enabling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add common function to enable PCI MMCONF base address. Use the common function in stoneyridge bootblock. Signed-off-by: Michał Żygowski Change-Id: I1bb8b22b282584c421a9fffa3322b2a8e406d037 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37552 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- .../block/include/amdblocks/amd_pci_mmconf.h | 19 +++++++++++++++ src/soc/amd/common/block/pci/Makefile.inc | 5 ++-- src/soc/amd/common/block/pci/amd_pci_mmconf.c | 27 ++++++++++++++++++++++ src/soc/amd/stoneyridge/bootblock/bootblock.c | 8 ++----- 4 files changed, 50 insertions(+), 9 deletions(-) create mode 100644 src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h create mode 100644 src/soc/amd/common/block/pci/amd_pci_mmconf.c (limited to 'src') diff --git a/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h new file mode 100644 index 0000000000..4b65ad0948 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/amd_pci_mmconf.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMDBLOCKS_PCI_MMCONF_H__ +#define __AMDBLOCKS_PCI_MMCONF_H__ + +void enable_pci_mmconf(void); + +#endif diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index fc40c9d478..558a7ac736 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,5 +1,4 @@ -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y) -ramstage-y += amd_pci_util.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c -endif +all-y += amd_pci_mmconf.c diff --git a/src/soc/amd/common/block/pci/amd_pci_mmconf.c b/src/soc/amd/common/block/pci/amd_pci_mmconf.c new file mode 100644 index 0000000000..1aed51bf1b --- /dev/null +++ b/src/soc/amd/common/block/pci/amd_pci_mmconf.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +void enable_pci_mmconf(void) +{ + msr_t mmconf; + + mmconf.hi = 0; + mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN + | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; + wrmsr(MMIO_CONF_BASE, mmconf); +} diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index d92535ac31..9920aff082 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -42,15 +43,9 @@ /* Set the MMIO Configuration Base Address, Bus Range, and misc MTRRs. */ static void amd_initmmio(void) { - msr_t mmconf; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int mtrr; - mmconf.hi = 0; - mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN - | fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT; - wrmsr(MMIO_CONF_BASE, mmconf); - /* * todo: AGESA currently writes variable MTRRs. Once that is * corrected, un-hardcode this MTRR. @@ -75,6 +70,7 @@ static void amd_initmmio(void) asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + enable_pci_mmconf(); amd_initmmio(); /* * Call lib/bootblock.c main with BSP, shortcut for APs -- cgit v1.2.3