From 1fa724b40c752704c0b9c54439a2d773af354088 Mon Sep 17 00:00:00 2001 From: Zhongze Hu Date: Fri, 16 Mar 2018 17:11:07 -0700 Subject: mb/google/fizz: Enable I2C bus 2 I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase it was idle. Google CFM add-in card is going to use this I2C bus so it needs to be re-enabled. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is working properly. Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808 Signed-off-by: Zhongze Hu Reviewed-on: https://review.coreboot.org/25258 Tested-by: build bot (Jenkins) Reviewed-by: Shelley Chen --- src/mainboard/google/fizz/devicetree.cb | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index d5ee04f716..a9646ec6cb 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -297,9 +297,9 @@ chip soc/intel/skylake # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, [PchSerialIoIndexI2C3] = PchSerialIoDisabled, [PchSerialIoIndexI2C4] = PchSerialIoDisabled, [PchSerialIoIndexI2C5] = PchSerialIoPci, @@ -330,9 +330,9 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem - device pci 15.0 off end # I2C #0 + device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 + device pci 15.2 on end # I2C #2 device pci 15.3 off end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 -- cgit v1.2.3