From 1d05a3bf56a63fc286719648f0c2c58a23dff80a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 21 Dec 2020 03:46:58 +0100 Subject: mb/intel/tglrvp: do UART pad config at board-level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UART pad configuration should not be done in common code, because that may cause short circuits, when the user sets a wrong UART index. Thus, add the corresponding pads to the early UART gpio table for the board as a first step. Common UART pad config code then gets dropped in CB:48829. Also switch to `bootblock_mainboard_early_init` to configure the pads in early bootblock before console initialization, to make the console work as early as possible. The board does not do any other gpio configuration in bootblock, so this should not influence behaviour in a negative way (e.g. breaking overrides). Change-Id: I130fd26944169430a84c3609432b1b5283581c99 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/49432 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/bootblock.c | 2 +- src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 4 ++++ src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c | 4 ++++ 3 files changed, 9 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/intel/tglrvp/bootblock.c b/src/mainboard/intel/tglrvp/bootblock.c index a8f7e41433..d7f3255974 100644 --- a/src/mainboard/intel/tglrvp/bootblock.c +++ b/src/mainboard/intel/tglrvp/bootblock.c @@ -5,7 +5,7 @@ #include #include -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { const struct pad_config *pads; size_t num; diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 51b301d3cf..448aa41ecc 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -63,6 +63,10 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ + /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 77da5cce5c..18dab082a2 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -59,6 +59,10 @@ static const struct pad_config gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* UART */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */ + /* Audio */ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_HP_SCLK */ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_HP_SFRM */ -- cgit v1.2.3