From 1cdce27cadb6239aca04192f28b74d976f2795d3 Mon Sep 17 00:00:00 2001 From: Hannah Williams Date: Tue, 5 Apr 2016 10:03:38 -0700 Subject: soc/apollolake: Enable Wake from USB devices Change-Id: Ib0b30a5779681488e80000a2570fc2fd4c69e908 Signed-off-by: Hannah Williams Reviewed-on: https://review.coreboot.org/14893 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/apollolake/acpi/southbridge.asl | 4 +++ src/soc/intel/apollolake/acpi/xhci.asl | 41 +++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpe.h | 37 ++++++++++++++++++++++++ 3 files changed, 82 insertions(+) create mode 100644 src/soc/intel/apollolake/acpi/xhci.asl create mode 100644 src/soc/intel/apollolake/include/soc/gpe.h (limited to 'src') diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 0584439a2a..9409d5e7d4 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -15,6 +15,8 @@ * GNU General Public License for more details. */ +#include + /* LPSS device */ #include "lpss.asl" @@ -23,3 +25,5 @@ /* GPIO controller */ #include "gpio.asl" + +#include "xhci.asl" diff --git a/src/soc/intel/apollolake/acpi/xhci.asl b/src/soc/intel/apollolake/acpi/xhci.asl new file mode 100644 index 0000000000..fc67074a8a --- /dev/null +++ b/src/soc/intel/apollolake/acpi/xhci.asl @@ -0,0 +1,41 @@ +/* This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* XHCI Controller 0:15.0 */ +Device(XHC1) { + Name(_ADR, 0x00150000) // Device 21, Function 0 + + Name (_S3D, 3) /* D3 supported in S3 */ + Name (_S0W, 3) /* D3 can wake device in S0 */ + Name (_S3W, 3) /* D3 can wake system from S3 */ + + // Declare XHCI GPE status and enable bits are bit 13 + Name (_PRW, Package() { GPE0A_XHCI_PME_STS, 3 }) + + Method (_DSW, 3, NotSerialized) // _DSW: Device Sleep Wake + { + Return (Zero) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + + Method(_STA, 0) + { + Return (0xF) + } + +} diff --git a/src/soc/intel/apollolake/include/soc/gpe.h b/src/soc/intel/apollolake/include/soc/gpe.h new file mode 100644 index 0000000000..8abbad86c6 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/gpe.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPE_H_ +#define _SOC_GPE_H_ + +/* bit position in GPE0a_STS register */ +#define GPE0A_PCIE_SCI_STS 0 +#define GPE0A_SWGPE_STS 2 +#define GPE0A_PCIE_WAKE0_STS 3 +#define GPE0A_PUNIT_SCI_STS 4 +#define GPE0A_PCIE_WAKE1_STS 6 +#define GPE0A_PCIE_WAKE2_STS 7 +#define GPE0A_PCIE_WAKE3_STS 8 +#define GPE0A_PCIE_GPE_STS 9 +#define GPE0A_BATLOW_STS 10 +#define GPE0A_CSE_PME_STS 11 +#define GPE0A_XDCI_PME_STS 12 +#define GPE0A_XHCI_PME_STS 13 +#define GPE0A_AVS_PME_STS 14 +#define GPE0A_GPIO_TIER1_SCI_STS 15 +#define GPE0A_SMB_WAK_STS 16 +#define GPE0A_SATA_PME_STS 17 + +#endif -- cgit v1.2.3