From 1b05d887d702fcf5ac704d2ee5257122a180694c Mon Sep 17 00:00:00 2001 From: Daisuke Nojiri Date: Wed, 27 Aug 2014 11:48:03 -0700 Subject: nyans: reduce code duplication in bootblock and romstages this change reduces the code duplication of the bootblock and the romstages for Nyans. BUG=none TEST=Built Nyan, Big, and Blaze. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: dnojiri@chromium.org (Daisuke Nojiri) Original-Change-Id: Ieb9dac3b061a2cf46c63afb2f31eb67ab391ea1a Original-Reviewed-on: https://chromium-review.googlesource.com/214050 Original-Reviewed-by: Julius Werner Original-Reviewed-by: Daisuke Nojiri Original-Commit-Queue: Daisuke Nojiri Original-Tested-by: Daisuke Nojiri (cherry picked from commit f3413d39458f03895fe4963a41285f71d81bcf5f) Signed-off-by: Aaron Durbin Change-Id: I912f63b12321aa26a7add302fc8a6c4e607330ef Reviewed-on: http://review.coreboot.org/8880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/google/nyan/Makefile.inc | 1 + src/mainboard/google/nyan/early_configs.c | 103 ++++++ src/mainboard/google/nyan/romstage.c | 121 +------ src/mainboard/google/nyan_big/Makefile.inc | 1 + src/mainboard/google/nyan_big/early_configs.c | 103 ++++++ src/mainboard/google/nyan_big/romstage.c | 121 +------ src/mainboard/google/nyan_blaze/Makefile.inc | 2 + src/mainboard/google/nyan_blaze/early_configs.c | 103 ++++++ src/mainboard/google/nyan_blaze/romstage.c | 121 +------ src/soc/nvidia/tegra124/Makefile.inc | 2 + src/soc/nvidia/tegra124/bootblock.c | 79 +---- src/soc/nvidia/tegra124/cache.c | 66 ++++ src/soc/nvidia/tegra124/cache.h | 20 ++ src/soc/nvidia/tegra124/early_configs.h | 20 ++ src/vendorcode/google/chromeos/Makefile.inc | 2 +- src/vendorcode/google/chromeos/vboot_main.c | 399 ------------------------ src/vendorcode/google/chromeos/verstage.c | 359 +++++++++++++++++++++ 17 files changed, 802 insertions(+), 821 deletions(-) create mode 100644 src/mainboard/google/nyan/early_configs.c create mode 100644 src/mainboard/google/nyan_big/early_configs.c create mode 100644 src/mainboard/google/nyan_blaze/early_configs.c create mode 100644 src/soc/nvidia/tegra124/cache.c create mode 100644 src/soc/nvidia/tegra124/cache.h create mode 100644 src/soc/nvidia/tegra124/early_configs.h delete mode 100644 src/vendorcode/google/chromeos/vboot_main.c create mode 100644 src/vendorcode/google/chromeos/verstage.c (limited to 'src') diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index ace6e32c0a..de1e127f59 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -36,6 +36,7 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += early_configs.c ramstage-y += boardid.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/nyan/early_configs.c b/src/mainboard/google/nyan/early_configs.c new file mode 100644 index 0000000000..c1f5f9b2f6 --- /dev/null +++ b/src/mainboard/google/nyan/early_configs.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void setup_pinmux(void) +{ + /* Write protect. */ + gpio_input_pullup(GPIO(R1)); + /* Recovery mode. */ + gpio_input_pullup(GPIO(Q7)); + /* Lid switch. */ + gpio_input_pullup(GPIO(R4)); + /* Power switch. */ + gpio_input_pullup(GPIO(Q0)); + /* Developer mode. */ + gpio_input_pullup(GPIO(Q6)); + /* EC in RW. */ + gpio_input_pullup(GPIO(U4)); + + /* route PU4/5 to GMI to remove conflict w/PWM1/2. */ + pinmux_set_config(PINMUX_GPIO_PU4_INDEX, + PINMUX_GPIO_PU4_FUNC_NOR); /* s/b GMI */ + pinmux_set_config(PINMUX_GPIO_PU5_INDEX, + PINMUX_GPIO_PU5_FUNC_NOR); /* s/b GMI */ + + /* SOC and TPM reset GPIO, active low. */ + gpio_output(GPIO(I5), 1); + + /* SPI1 MOSI */ + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + /* SPI1 MISO */ + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + /* SPI1 SCLK */ + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + /* SPI1 CS0 */ + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + + /* I2C3 (cam) clock. */ + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + /* I2C3 (cam) data. */ + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + + /* switch unused pin to GPIO */ + gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); +} + +static void configure_ec_spi_bus(void) +{ + clock_configure_source(sbc1, CLK_M, 3000); +} + +static void configure_tpm_i2c_bus(void) +{ + clock_configure_i2c_scl_freq(i2c3, PLLP, 400); + + i2c_init(2); +} + +void early_mainboard_init(void) +{ + clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); + setup_pinmux(); + configure_ec_spi_bus(); + configure_tpm_i2c_bus(); +} diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 914c925d5d..0baf2b74f8 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -30,8 +30,10 @@ #include #include "sdram_configs.h" #include +#include #include #include +#include #include #include #include @@ -39,120 +41,12 @@ #include #include -static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; - -enum { - L2CTLR_ECC_PARITY = 0x1 << 21, - L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, - L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, - L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, - L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 -}; - -enum { - L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, - L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, - L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 -}; - -/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ -static void configure_l2ctlr(void) -{ - uint32_t val; - - val = read_l2ctlr(); - val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); - val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | - L2CTLR_ECC_PARITY); - write_l2ctlr(val); -} - -/* Configures L2 Auxiliary Control Register for Cortex A15. */ -static void configure_l2actlr(void) -{ - uint32_t val; - - val = read_l2actlr(); - val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | - L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | - L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); - write_l2actlr(val); -} - -static void setup_pinmux(void) -{ - // Write protect. - gpio_input_pullup(GPIO(R1)); - // Recovery mode. - gpio_input_pullup(GPIO(Q7)); - // Lid switch. - gpio_input_pullup(GPIO(R4)); - // Power switch. - gpio_input_pullup(GPIO(Q0)); - // Developer mode. - gpio_input_pullup(GPIO(Q6)); - // EC in RW. - gpio_input_pullup(GPIO(U4)); - - // route PU4/5 to GMI to remove conflict w/PWM1/2. - pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI - pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI - - // SOC and TPM reset GPIO, active low. - gpio_output(GPIO(I5), 1); - - // SPI1 MOSI - pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 MISO - pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 SCLK - pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 CS0 - pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - - // I2C3 (cam) clock. - pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, - PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - // I2C3 (cam) data. - pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, - PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - - // switch unused pin to GPIO - gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); -} - -static void configure_ec_spi_bus(void) -{ - clock_configure_source(sbc1, CLK_M, 3000); -} - -static void configure_tpm_i2c_bus(void) -{ - clock_configure_i2c_scl_freq(i2c3, PLLP, 400); - - i2c_init(2); -} - static void __attribute__((noinline)) romstage(void) { timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); - configure_l2ctlr(); - configure_l2actlr(); + configure_l2_cache(); console_init(); exception_init(); @@ -191,13 +85,10 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - // Enable additional peripherals we need for ROM stage. - clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); - - setup_pinmux(); + timestamp_init(0); + timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - configure_ec_spi_bus(); - configure_tpm_i2c_bus(); + early_mainboard_init(); vboot_verify_firmware(romstage_handoff_find_or_add()); diff --git a/src/mainboard/google/nyan_big/Makefile.inc b/src/mainboard/google/nyan_big/Makefile.inc index 59a165336e..1eb54042c4 100644 --- a/src/mainboard/google/nyan_big/Makefile.inc +++ b/src/mainboard/google/nyan_big/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += early_configs.c ramstage-y += boardid.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/nyan_big/early_configs.c b/src/mainboard/google/nyan_big/early_configs.c new file mode 100644 index 0000000000..c1f5f9b2f6 --- /dev/null +++ b/src/mainboard/google/nyan_big/early_configs.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void setup_pinmux(void) +{ + /* Write protect. */ + gpio_input_pullup(GPIO(R1)); + /* Recovery mode. */ + gpio_input_pullup(GPIO(Q7)); + /* Lid switch. */ + gpio_input_pullup(GPIO(R4)); + /* Power switch. */ + gpio_input_pullup(GPIO(Q0)); + /* Developer mode. */ + gpio_input_pullup(GPIO(Q6)); + /* EC in RW. */ + gpio_input_pullup(GPIO(U4)); + + /* route PU4/5 to GMI to remove conflict w/PWM1/2. */ + pinmux_set_config(PINMUX_GPIO_PU4_INDEX, + PINMUX_GPIO_PU4_FUNC_NOR); /* s/b GMI */ + pinmux_set_config(PINMUX_GPIO_PU5_INDEX, + PINMUX_GPIO_PU5_FUNC_NOR); /* s/b GMI */ + + /* SOC and TPM reset GPIO, active low. */ + gpio_output(GPIO(I5), 1); + + /* SPI1 MOSI */ + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + /* SPI1 MISO */ + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + /* SPI1 SCLK */ + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + /* SPI1 CS0 */ + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + + /* I2C3 (cam) clock. */ + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + /* I2C3 (cam) data. */ + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + + /* switch unused pin to GPIO */ + gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); +} + +static void configure_ec_spi_bus(void) +{ + clock_configure_source(sbc1, CLK_M, 3000); +} + +static void configure_tpm_i2c_bus(void) +{ + clock_configure_i2c_scl_freq(i2c3, PLLP, 400); + + i2c_init(2); +} + +void early_mainboard_init(void) +{ + clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); + setup_pinmux(); + configure_ec_spi_bus(); + configure_tpm_i2c_bus(); +} diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 914c925d5d..0baf2b74f8 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -30,8 +30,10 @@ #include #include "sdram_configs.h" #include +#include #include #include +#include #include #include #include @@ -39,120 +41,12 @@ #include #include -static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; - -enum { - L2CTLR_ECC_PARITY = 0x1 << 21, - L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, - L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, - L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, - L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 -}; - -enum { - L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, - L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, - L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 -}; - -/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ -static void configure_l2ctlr(void) -{ - uint32_t val; - - val = read_l2ctlr(); - val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); - val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | - L2CTLR_ECC_PARITY); - write_l2ctlr(val); -} - -/* Configures L2 Auxiliary Control Register for Cortex A15. */ -static void configure_l2actlr(void) -{ - uint32_t val; - - val = read_l2actlr(); - val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | - L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | - L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); - write_l2actlr(val); -} - -static void setup_pinmux(void) -{ - // Write protect. - gpio_input_pullup(GPIO(R1)); - // Recovery mode. - gpio_input_pullup(GPIO(Q7)); - // Lid switch. - gpio_input_pullup(GPIO(R4)); - // Power switch. - gpio_input_pullup(GPIO(Q0)); - // Developer mode. - gpio_input_pullup(GPIO(Q6)); - // EC in RW. - gpio_input_pullup(GPIO(U4)); - - // route PU4/5 to GMI to remove conflict w/PWM1/2. - pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI - pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI - - // SOC and TPM reset GPIO, active low. - gpio_output(GPIO(I5), 1); - - // SPI1 MOSI - pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 MISO - pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 SCLK - pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 CS0 - pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - - // I2C3 (cam) clock. - pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, - PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - // I2C3 (cam) data. - pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, - PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - - // switch unused pin to GPIO - gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); -} - -static void configure_ec_spi_bus(void) -{ - clock_configure_source(sbc1, CLK_M, 3000); -} - -static void configure_tpm_i2c_bus(void) -{ - clock_configure_i2c_scl_freq(i2c3, PLLP, 400); - - i2c_init(2); -} - static void __attribute__((noinline)) romstage(void) { timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); - configure_l2ctlr(); - configure_l2actlr(); + configure_l2_cache(); console_init(); exception_init(); @@ -191,13 +85,10 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - // Enable additional peripherals we need for ROM stage. - clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); - - setup_pinmux(); + timestamp_init(0); + timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - configure_ec_spi_bus(); - configure_tpm_i2c_bus(); + early_mainboard_init(); vboot_verify_firmware(romstage_handoff_find_or_add()); diff --git a/src/mainboard/google/nyan_blaze/Makefile.inc b/src/mainboard/google/nyan_blaze/Makefile.inc index 2630dc5327..daf9039a32 100644 --- a/src/mainboard/google/nyan_blaze/Makefile.inc +++ b/src/mainboard/google/nyan_blaze/Makefile.inc @@ -30,10 +30,12 @@ subdirs-y += bct bootblock-y += bootblock.c bootblock-y += pmic.c bootblock-y += reset.c +bootblock-y += early_configs.c verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-y += reset.c +romstage-y += early_configs.c romstage-y += reset.c romstage-y += romstage.c romstage-y += sdram_configs.c diff --git a/src/mainboard/google/nyan_blaze/early_configs.c b/src/mainboard/google/nyan_blaze/early_configs.c new file mode 100644 index 0000000000..c1f5f9b2f6 --- /dev/null +++ b/src/mainboard/google/nyan_blaze/early_configs.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void setup_pinmux(void) +{ + /* Write protect. */ + gpio_input_pullup(GPIO(R1)); + /* Recovery mode. */ + gpio_input_pullup(GPIO(Q7)); + /* Lid switch. */ + gpio_input_pullup(GPIO(R4)); + /* Power switch. */ + gpio_input_pullup(GPIO(Q0)); + /* Developer mode. */ + gpio_input_pullup(GPIO(Q6)); + /* EC in RW. */ + gpio_input_pullup(GPIO(U4)); + + /* route PU4/5 to GMI to remove conflict w/PWM1/2. */ + pinmux_set_config(PINMUX_GPIO_PU4_INDEX, + PINMUX_GPIO_PU4_FUNC_NOR); /* s/b GMI */ + pinmux_set_config(PINMUX_GPIO_PU5_INDEX, + PINMUX_GPIO_PU5_FUNC_NOR); /* s/b GMI */ + + /* SOC and TPM reset GPIO, active low. */ + gpio_output(GPIO(I5), 1); + + /* SPI1 MOSI */ + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + /* SPI1 MISO */ + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + /* SPI1 SCLK */ + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + /* SPI1 CS0 */ + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + + /* I2C3 (cam) clock. */ + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + /* I2C3 (cam) data. */ + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + + /* switch unused pin to GPIO */ + gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); + gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); +} + +static void configure_ec_spi_bus(void) +{ + clock_configure_source(sbc1, CLK_M, 3000); +} + +static void configure_tpm_i2c_bus(void) +{ + clock_configure_i2c_scl_freq(i2c3, PLLP, 400); + + i2c_init(2); +} + +void early_mainboard_init(void) +{ + clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); + setup_pinmux(); + configure_ec_spi_bus(); + configure_tpm_i2c_bus(); +} diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index a0dde9e615..cfeb77a523 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -30,8 +30,10 @@ #include #include "sdram_configs.h" #include +#include #include #include +#include #include #include #include @@ -39,120 +41,12 @@ #include #include -static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; - -enum { - L2CTLR_ECC_PARITY = 0x1 << 21, - L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, - L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, - L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, - L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 -}; - -enum { - L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, - L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, - L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 -}; - -/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ -static void configure_l2ctlr(void) -{ - uint32_t val; - - val = read_l2ctlr(); - val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); - val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | - L2CTLR_ECC_PARITY); - write_l2ctlr(val); -} - -/* Configures L2 Auxiliary Control Register for Cortex A15. */ -static void configure_l2actlr(void) -{ - uint32_t val; - - val = read_l2actlr(); - val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | - L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | - L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); - write_l2actlr(val); -} - -static void setup_pinmux(void) -{ - // Write protect. - gpio_input_pullup(GPIO(R1)); - // Recovery mode. - gpio_input_pullup(GPIO(Q7)); - // Lid switch. - gpio_input_pullup(GPIO(R4)); - // Power switch. - gpio_input_pullup(GPIO(Q0)); - // Developer mode. - gpio_input_pullup(GPIO(Q6)); - // EC in RW. - gpio_input_pullup(GPIO(U4)); - - // route PU4/5 to GMI to remove conflict w/PWM1/2. - pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); //s/b GMI - pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); //s/b GMI - - // SOC and TPM reset GPIO, active low. - gpio_output(GPIO(I5), 1); - - // SPI1 MOSI - pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 MISO - pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 SCLK - pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 CS0 - pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - - // I2C3 (cam) clock. - pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, - PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - // I2C3 (cam) data. - pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, - PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - - // switch unused pin to GPIO - gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); -} - -static void configure_ec_spi_bus(void) -{ - clock_configure_source(sbc1, CLK_M, 3000); -} - -static void configure_tpm_i2c_bus(void) -{ - clock_configure_i2c_scl_freq(i2c3, PLLP, 400); - - i2c_init(2); -} - static void __attribute__((noinline)) romstage(void) { timestamp_init(0); timestamp_add_now(TS_START_ROMSTAGE); - configure_l2ctlr(); - configure_l2actlr(); + configure_l2_cache(); console_init(); exception_init(); @@ -191,13 +85,10 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - // Enable additional peripherals we need for ROM stage. - clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); - - setup_pinmux(); + timestamp_init(0); + timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - configure_ec_spi_bus(); - configure_tpm_i2c_bus(); + early_mainboard_init(); #if CONFIG_VBOOT2_VERIFY_FIRMWARE vboot_create_handoff((void *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS); diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 8966168a78..d32580e96b 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -32,6 +32,7 @@ verstage-y += ../tegra/i2c.c verstage-y += ../tegra/pinmux.c verstage-y += clock.c verstage-y += i2c.c +verstage-y += cache.c romstage-y += cbfs.c romstage-y += cbmem.c @@ -48,6 +49,7 @@ romstage-y += ../tegra/i2c.c romstage-$(CONFIG_SOFTWARE_I2C) += ../tegra/software_i2c.c romstage-y += ../tegra/pinmux.c romstage-y += timer.c +romstage-y += cache.c romstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cbfs.c diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 22e7ba8557..1d18f1e4cf 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -25,81 +25,11 @@ #include #include #include +#include +#include #include "pinmux.h" #include "power.h" #include "verstage.h" -#include -#include -#include -#include -static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; - -static void setup_pinmux(void) -{ - // Write protect. - gpio_input_pullup(GPIO(R1)); - // Recovery mode. - gpio_input_pullup(GPIO(Q7)); - // Lid switch. - gpio_input_pullup(GPIO(R4)); - // Power switch. - gpio_input_pullup(GPIO(Q0)); - // Developer mode. - gpio_input_pullup(GPIO(Q6)); - // EC in RW. - gpio_input_pullup(GPIO(U4)); - - // route PU4/5 to GMI to remove conflict w/PWM1/2. - pinmux_set_config(PINMUX_GPIO_PU4_INDEX, PINMUX_GPIO_PU4_FUNC_NOR); - pinmux_set_config(PINMUX_GPIO_PU5_INDEX, PINMUX_GPIO_PU5_FUNC_NOR); - - // SOC and TPM reset GPIO, active low. - gpio_output(GPIO(I5), 1); - - // SPI1 MOSI - pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 MISO - pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 SCLK - pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - // SPI1 CS0 - pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | - PINMUX_PULL_NONE | - PINMUX_INPUT_ENABLE); - - // I2C3 (cam) clock. - pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, - PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - // I2C3 (cam) data. - pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, - PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - - // switch unused pin to GPIO - gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO); - gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO); -} - -static void configure_ec_spi_bus(void) -{ - clock_configure_source(sbc1, CLK_M, 3000); -} - -static void configure_tpm_i2c_bus(void) -{ - clock_configure_i2c_scl_freq(i2c3, PLLP, 400); - - i2c_init(2); -} void main(void) { @@ -144,10 +74,7 @@ void main(void) PINMUX_INPUT_ENABLE); if (IS_ENABLED(CONFIG_VBOOT2_VERIFY_FIRMWARE)) { - clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); - setup_pinmux(); - configure_ec_spi_bus(); - configure_tpm_i2c_bus(); + early_mainboard_init(); entry = (void *)verstage_vboot_main; } else entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); diff --git a/src/soc/nvidia/tegra124/cache.c b/src/soc/nvidia/tegra124/cache.c new file mode 100644 index 0000000000..55e625478a --- /dev/null +++ b/src/soc/nvidia/tegra124/cache.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include "cache.h" + +enum { + L2CTLR_ECC_PARITY = 0x1 << 21, + L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, + L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, + L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, + L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 +}; + +enum { + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, + L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 +}; + +/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ +static void configure_l2ctlr(void) +{ + uint32_t val; + + val = read_l2ctlr(); + val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); + val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | + L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | L2CTLR_ECC_PARITY); + write_l2ctlr(val); +} + +/* Configures L2 Auxiliary Control Register for Cortex A15. */ +static void configure_l2actlr(void) +{ + uint32_t val; + + val = read_l2actlr(); + val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); + write_l2actlr(val); +} + +void configure_l2_cache(void) +{ + configure_l2ctlr(); + configure_l2actlr(); +} diff --git a/src/soc/nvidia/tegra124/cache.h b/src/soc/nvidia/tegra124/cache.h new file mode 100644 index 0000000000..3723cd7650 --- /dev/null +++ b/src/soc/nvidia/tegra124/cache.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void configure_l2_cache(void); diff --git a/src/soc/nvidia/tegra124/early_configs.h b/src/soc/nvidia/tegra124/early_configs.h new file mode 100644 index 0000000000..69511d2765 --- /dev/null +++ b/src/soc/nvidia/tegra124/early_configs.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +void early_mainboard_init(void); diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 32a76b9e47..701feb7b7f 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -101,7 +101,7 @@ VERSTAGE_LIB = $(obj)/vendorcode/google/chromeos/verstage.a INCLUDES += -I$(VB_SOURCE)/firmware/2lib/include INCLUDES += -I$(VB_SOURCE)/firmware/include -verstage-y += vboot_main.c fmap.c chromeos.c +verstage-y += verstage.c fmap.c chromeos.c verstage-y += antirollback.c vbnv_ec.c romstage-y += vboot_handoff.c diff --git a/src/vendorcode/google/chromeos/vboot_main.c b/src/vendorcode/google/chromeos/vboot_main.c deleted file mode 100644 index 252dfb1bf8..0000000000 --- a/src/vendorcode/google/chromeos/vboot_main.c +++ /dev/null @@ -1,399 +0,0 @@ -#include <2api.h> -#include <2struct.h> -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "chromeos.h" -#include "fmap.h" - -#define VBDEBUG(format, args...) \ - printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) -#define TODO_BLOCK_SIZE 8192 -#define MAX_PARSED_FW_COMPONENTS 5 -#define ROMSTAGE_INDEX 2 - -struct component_entry { - uint32_t offset; - uint32_t size; -} __attribute__((packed)); - -struct components { - uint32_t num_components; - struct component_entry entries[MAX_PARSED_FW_COMPONENTS]; -} __attribute__((packed)); - -struct vboot_region { - uintptr_t offset_addr; - int32_t size; -}; - -static void locate_region(const char *name, struct vboot_region *region) -{ - region->size = find_fmap_entry(name, (void **)®ion->offset_addr); - VBDEBUG("Located %s @%x\n", name, region->offset_addr); -} - -static int is_slot_a(struct vb2_context *ctx) -{ - return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); -} - -static int in_ro(void) -{ - /* TODO: Implement */ - return 1; -} - -/* exports */ - -void vb2ex_printf(const char *func, const char *fmt, ...) -{ - va_list args; - - printk(BIOS_INFO, "VB2:%s() ", func); - va_start(args, fmt); - printk(BIOS_INFO, fmt, args); - va_end(args); - - return; -} - -int vb2ex_tpm_clear_owner(struct vb2_context *ctx) -{ - uint32_t rv; - VBDEBUG("Clearing TPM owner\n"); - rv = tpm_clear_and_reenable(); - if (rv) - return VB2_ERROR_EX_TPM_CLEAR_OWNER; - return VB2_SUCCESS; -} - -int vb2ex_read_resource(struct vb2_context *ctx, - enum vb2_resource_index index, - uint32_t offset, - void *buf, - uint32_t size) -{ - struct vboot_region region; - - switch (index) { - case VB2_RES_GBB: - locate_region("GBB", ®ion); - break; - case VB2_RES_FW_VBLOCK: - if (is_slot_a(ctx)) - locate_region("VBLOCK_A", ®ion); - else - locate_region("VBLOCK_B", ®ion); - break; - default: - return VB2_ERROR_EX_READ_RESOURCE_INDEX; - } - - if (offset + size > region.size) - return VB2_ERROR_EX_READ_RESOURCE_SIZE; - - if (vboot_get_region(region.offset_addr + offset, size, buf) == NULL) - return VB2_ERROR_UNKNOWN; - - return VB2_SUCCESS; -} - -static void reboot(void) -{ - cpu_reset(); -} - -static void recovery(void) -{ - void *entry; - - if (!in_ro()) - reboot(); - - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); - if (entry != (void *)-1) - stage_exit(entry); - - for(;;); -} - -static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main) -{ - uint32_t expected_size; - uint8_t block[TODO_BLOCK_SIZE]; - size_t block_size = sizeof(block); - uintptr_t offset; - int rv; - - expected_size = fw_main->size; - offset= fw_main->offset_addr; - - /* Start the body hash */ - rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size); - if (rv) { - return rv; - } - - /* Extend over the body */ - while (expected_size) { - void *b; - if (block_size > expected_size) - block_size = expected_size; - - b = vboot_get_region(offset, block_size, block); - if (b == NULL) - return VB2_ERROR_UNKNOWN; - rv = vb2api_extend_hash(ctx, b, block_size); - if (rv) - return rv; - - expected_size -= block_size; - offset+= block_size; - } - - /* Check the result */ - rv = vb2api_check_hash(ctx); - if (rv) { - return rv; - } - - return VB2_SUCCESS; -} - -static int locate_fw_components(struct vb2_context *ctx, - struct vboot_region *fw_main, - struct components *fw_info) -{ - if (is_slot_a(ctx)) - locate_region("FW_MAIN_A", fw_main); - else - locate_region("FW_MAIN_B", fw_main); - if (fw_main->size < 0) - return 1; - - if (vboot_get_region(fw_main->offset_addr, - sizeof(*fw_info), fw_info) == NULL) - return 1; - return 0; -} - -static struct cbfs_stage *load_stage(struct vb2_context *ctx, - int stage_index, - struct vboot_region *fw_main, - struct components *fw_info) -{ - struct cbfs_stage *stage; - uint32_t fc_addr; - uint32_t fc_size; - - /* Check for invalid address. */ - fc_addr = fw_main->offset_addr + fw_info->entries[stage_index].offset; - fc_size = fw_info->entries[stage_index].size; - if (fc_addr == 0 || fc_size == 0) { - VBDEBUG("romstage address invalid.\n"); - return NULL; - } - - /* Loading to cbfs cache. This stage data must be retained until it's - * decompressed. */ - stage = vboot_get_region(fc_addr, fc_size, NULL); - - if (stage == NULL) { - VBDEBUG("Unable to load a stage.\n"); - return NULL; - } - - return stage; -} - -static void enter_stage(struct cbfs_stage *stage) -{ - /* Stages rely the below clearing so that the bss is initialized. */ - memset((void *) (uintptr_t)stage->load, 0, stage->memlen); - - if (cbfs_decompress(stage->compression, - (unsigned char *)stage + sizeof(*stage), - (void *) (uintptr_t) stage->load, - stage->len)) - return; - - VBDEBUG("Jumping to entry @%llx.\n", stage->entry); - stage_exit((void *)(uintptr_t)stage->entry); -} - -enum { - L2CTLR_ECC_PARITY = 0x1 << 21, - L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, - L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, - L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, - L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 -}; - -enum { - L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, - L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, - L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 -}; - -/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ -static void configure_l2ctlr(void) -{ - uint32_t val; - - val = read_l2ctlr(); - val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); - val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | - L2CTLR_ECC_PARITY); - write_l2ctlr(val); -} - -/* Configures L2 Auxiliary Control Register for Cortex A15. */ -static void configure_l2actlr(void) -{ - uint32_t val; - - val = read_l2actlr(); - val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | - L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | - L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); - write_l2actlr(val); -} - -static void enable_cache(void) -{ - mmu_init(); - mmu_config_range(0, CONFIG_SYS_SDRAM_BASE >> 20, DCACHE_OFF); - mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); - mmu_disable_range(0, 1); - VBDEBUG("Enabling cache\n"); - dcache_mmu_enable(); -} - -/** - * Save non-volatile and/or secure data if needed. - */ -static void save_if_needed(struct vb2_context *ctx) -{ - if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { - VBDEBUG("Saving nvdata\n"); - save_vbnv(ctx->nvdata); - ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; - } - if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { - VBDEBUG("Saving secdata\n"); - antirollback_write_space_firmware(ctx); - ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED; - } -} - -/** - * Load and verify the next stage from RW image and jump to it - * - * If validation fails, it exits to romstage for recovery or reboots. - * - * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage). - * when per-stage verification is ready. - */ -void __attribute__((noinline)) select_firmware(void) -{ - struct vb2_context ctx; - uint8_t *workbuf = (uint8_t *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS; - struct vboot_region fw_main; - struct components fw_info; - struct cbfs_stage *stage; - int rv; - - /* Do minimum to enable cache and run vboot at full speed */ - configure_l2ctlr(); - configure_l2actlr(); - console_init(); - exception_init(); - enable_cache(); - - /* Set up context */ - memset(&ctx, 0, sizeof(ctx)); - ctx.workbuf = workbuf; - ctx.workbuf_size = CONFIG_VBOOT_WORK_BUFFER_SIZE; - memset(ctx.workbuf, 0, ctx.workbuf_size); - - /* Read nvdata from a non-volatile storage */ - read_vbnv(ctx.nvdata); - - /* Read secdata from TPM. Initialize TPM if secdata not found. We don't - * check the return value here because vb2api_fw_phase1 will catch - * invalid secdata and tell us what to do (=reboot). */ - antirollback_read_space_firmware(&ctx); - - if (get_developer_mode_switch()) - ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; - if (get_recovery_mode_switch()) { - clear_recovery_mode_switch(); - ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; - } - - /* Do early init */ - VBDEBUG("Phase 1\n"); - rv = vb2api_fw_phase1(&ctx); - if (rv) { - VBDEBUG("Recovery requested (%x)\n", rv); - /* If we need recovery mode, leave firmware selection now */ - save_if_needed(&ctx); - recovery(); - } - - /* Determine which firmware slot to boot */ - VBDEBUG("Phase 2\n"); - rv = vb2api_fw_phase2(&ctx); - if (rv) { - VBDEBUG("Reboot requested (%x)\n", rv); - save_if_needed(&ctx); - reboot(); - } - - /* Try that slot */ - VBDEBUG("Phase 3\n"); - rv = vb2api_fw_phase3(&ctx); - if (rv) { - VBDEBUG("Reboot requested (%x)\n", rv); - save_if_needed(&ctx); - reboot(); - } - - VBDEBUG("Phase 4\n"); - rv = locate_fw_components(&ctx, &fw_main, &fw_info); - if (rv) { - VBDEBUG("Failed to locate firmware components\n"); - reboot(); - } - rv = hash_body(&ctx, &fw_main); - stage = load_stage(&ctx, ROMSTAGE_INDEX, &fw_main, &fw_info); - if (stage == NULL) { - VBDEBUG("Failed to load stage\n"); - reboot(); - } - save_if_needed(&ctx); - if (rv) { - VBDEBUG("Reboot requested (%x)\n", rv); - reboot(); - } - - /* TODO: Do we need to lock secdata? */ - VBDEBUG("Locking TPM\n"); - - /* Load next stage and jump to it */ - VBDEBUG("Jumping to rw-romstage @%llx\n", stage->entry); - enter_stage(stage); - - /* Shouldn't reach here */ - VBDEBUG("Halting\n"); - for(;;); -} diff --git a/src/vendorcode/google/chromeos/verstage.c b/src/vendorcode/google/chromeos/verstage.c new file mode 100644 index 0000000000..1564d8031b --- /dev/null +++ b/src/vendorcode/google/chromeos/verstage.c @@ -0,0 +1,359 @@ +#include <2api.h> +#include <2struct.h> +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chromeos.h" +#include "fmap.h" + +#define VBDEBUG(format, args...) \ + printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) +#define TODO_BLOCK_SIZE 8192 +#define MAX_PARSED_FW_COMPONENTS 5 +#define ROMSTAGE_INDEX 2 + +struct component_entry { + uint32_t offset; + uint32_t size; +} __attribute__((packed)); + +struct components { + uint32_t num_components; + struct component_entry entries[MAX_PARSED_FW_COMPONENTS]; +} __attribute__((packed)); + +struct vboot_region { + uintptr_t offset_addr; + int32_t size; +}; + +static void locate_region(const char *name, struct vboot_region *region) +{ + region->size = find_fmap_entry(name, (void **)®ion->offset_addr); + VBDEBUG("Located %s @%x\n", name, region->offset_addr); +} + +static int is_slot_a(struct vb2_context *ctx) +{ + return !(ctx->flags & VB2_CONTEXT_FW_SLOT_B); +} + +static int in_ro(void) +{ + /* TODO: Implement */ + return 1; +} + +/* exports */ + +void vb2ex_printf(const char *func, const char *fmt, ...) +{ + va_list args; + + printk(BIOS_INFO, "VB2:%s() ", func); + va_start(args, fmt); + printk(BIOS_INFO, fmt, args); + va_end(args); + + return; +} + +int vb2ex_tpm_clear_owner(struct vb2_context *ctx) +{ + uint32_t rv; + VBDEBUG("Clearing TPM owner\n"); + rv = tpm_clear_and_reenable(); + if (rv) + return VB2_ERROR_EX_TPM_CLEAR_OWNER; + return VB2_SUCCESS; +} + +int vb2ex_read_resource(struct vb2_context *ctx, + enum vb2_resource_index index, + uint32_t offset, + void *buf, + uint32_t size) +{ + struct vboot_region region; + + switch (index) { + case VB2_RES_GBB: + locate_region("GBB", ®ion); + break; + case VB2_RES_FW_VBLOCK: + if (is_slot_a(ctx)) + locate_region("VBLOCK_A", ®ion); + else + locate_region("VBLOCK_B", ®ion); + break; + default: + return VB2_ERROR_EX_READ_RESOURCE_INDEX; + } + + if (offset + size > region.size) + return VB2_ERROR_EX_READ_RESOURCE_SIZE; + + if (vboot_get_region(region.offset_addr + offset, size, buf) == NULL) + return VB2_ERROR_UNKNOWN; + + return VB2_SUCCESS; +} + +static void reboot(void) +{ + cpu_reset(); +} + +static void recovery(void) +{ + void *entry; + + if (!in_ro()) + reboot(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + if (entry != (void *)-1) + stage_exit(entry); + + for (;;); +} + +static int hash_body(struct vb2_context *ctx, struct vboot_region *fw_main) +{ + uint32_t expected_size; + uint8_t block[TODO_BLOCK_SIZE]; + size_t block_size = sizeof(block); + uintptr_t offset; + int rv; + + expected_size = fw_main->size; + offset = fw_main->offset_addr; + + /* Start the body hash */ + rv = vb2api_init_hash(ctx, VB2_HASH_TAG_FW_BODY, &expected_size); + if (rv) + return rv; + + /* Extend over the body */ + while (expected_size) { + void *b; + if (block_size > expected_size) + block_size = expected_size; + + b = vboot_get_region(offset, block_size, block); + if (b == NULL) + return VB2_ERROR_UNKNOWN; + rv = vb2api_extend_hash(ctx, b, block_size); + if (rv) + return rv; + + expected_size -= block_size; + offset += block_size; + } + + /* Check the result */ + rv = vb2api_check_hash(ctx); + if (rv) + return rv; + + return VB2_SUCCESS; +} + +static int locate_fw_components(struct vb2_context *ctx, + struct vboot_region *fw_main, + struct components *fw_info) +{ + if (is_slot_a(ctx)) + locate_region("FW_MAIN_A", fw_main); + else + locate_region("FW_MAIN_B", fw_main); + if (fw_main->size < 0) + return 1; + + if (vboot_get_region(fw_main->offset_addr, + sizeof(*fw_info), fw_info) == NULL) + return 1; + return 0; +} + +static struct cbfs_stage *load_stage(struct vb2_context *ctx, + int stage_index, + struct vboot_region *fw_main, + struct components *fw_info) +{ + struct cbfs_stage *stage; + uint32_t fc_addr; + uint32_t fc_size; + + /* Check for invalid address. */ + fc_addr = fw_main->offset_addr + fw_info->entries[stage_index].offset; + fc_size = fw_info->entries[stage_index].size; + if (fc_addr == 0 || fc_size == 0) { + VBDEBUG("romstage address invalid.\n"); + return NULL; + } + + /* Loading to cbfs cache. This stage data must be retained until it's + * decompressed. */ + stage = vboot_get_region(fc_addr, fc_size, NULL); + + if (stage == NULL) { + VBDEBUG("Unable to load a stage.\n"); + return NULL; + } + + return stage; +} + +static void enter_stage(struct cbfs_stage *stage) +{ + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *) (uintptr_t)stage->load, 0, stage->memlen); + + if (cbfs_decompress(stage->compression, + (unsigned char *)stage + sizeof(*stage), + (void *) (uintptr_t) stage->load, + stage->len)) + return; + + VBDEBUG("Jumping to entry @%llx.\n", stage->entry); + stage_exit((void *)(uintptr_t)stage->entry); +} + +static void enable_cache(void) +{ + mmu_init(); + mmu_config_range(0, CONFIG_SYS_SDRAM_BASE >> 20, DCACHE_OFF); + mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK); + mmu_disable_range(0, 1); + VBDEBUG("Enabling cache\n"); + dcache_mmu_enable(); +} + +/** + * Save non-volatile and/or secure data if needed. + */ +static void save_if_needed(struct vb2_context *ctx) +{ + if (ctx->flags & VB2_CONTEXT_NVDATA_CHANGED) { + VBDEBUG("Saving nvdata\n"); + save_vbnv(ctx->nvdata); + ctx->flags &= ~VB2_CONTEXT_NVDATA_CHANGED; + } + if (ctx->flags & VB2_CONTEXT_SECDATA_CHANGED) { + VBDEBUG("Saving secdata\n"); + antirollback_write_space_firmware(ctx); + ctx->flags &= ~VB2_CONTEXT_SECDATA_CHANGED; + } +} + +/** + * Load and verify the next stage from RW image and jump to it + * + * If validation fails, it exits to romstage for recovery or reboots. + * + * TODO: Avoid loading a stage twice (once in hash_body & again in load_stage). + * when per-stage verification is ready. + */ +void __attribute__((noinline)) select_firmware(void) +{ + struct vb2_context ctx; + uint8_t *workbuf = (uint8_t *)CONFIG_VBOOT_WORK_BUFFER_ADDRESS; + struct vboot_region fw_main; + struct components fw_info; + struct cbfs_stage *stage; + int rv; + + /* Do minimum to enable cache and run vboot at full speed */ + configure_l2_cache(); + console_init(); + exception_init(); + enable_cache(); + + /* Set up context */ + memset(&ctx, 0, sizeof(ctx)); + ctx.workbuf = workbuf; + ctx.workbuf_size = CONFIG_VBOOT_WORK_BUFFER_SIZE; + memset(ctx.workbuf, 0, ctx.workbuf_size); + + /* Read nvdata from a non-volatile storage */ + read_vbnv(ctx.nvdata); + + /* Read secdata from TPM. Initialize TPM if secdata not found. We don't + * check the return value here because vb2api_fw_phase1 will catch + * invalid secdata and tell us what to do (=reboot). */ + antirollback_read_space_firmware(&ctx); + + if (get_developer_mode_switch()) + ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE; + if (get_recovery_mode_switch()) { + clear_recovery_mode_switch(); + ctx.flags |= VB2_CONTEXT_FORCE_RECOVERY_MODE; + } + + /* Do early init */ + VBDEBUG("Phase 1\n"); + rv = vb2api_fw_phase1(&ctx); + if (rv) { + VBDEBUG("Recovery requested (%x)\n", rv); + /* If we need recovery mode, leave firmware selection now */ + save_if_needed(&ctx); + recovery(); + } + + /* Determine which firmware slot to boot */ + VBDEBUG("Phase 2\n"); + rv = vb2api_fw_phase2(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + save_if_needed(&ctx); + reboot(); + } + + /* Try that slot */ + VBDEBUG("Phase 3\n"); + rv = vb2api_fw_phase3(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + save_if_needed(&ctx); + reboot(); + } + + VBDEBUG("Phase 4\n"); + rv = locate_fw_components(&ctx, &fw_main, &fw_info); + if (rv) { + VBDEBUG("Failed to locate firmware components\n"); + reboot(); + } + rv = hash_body(&ctx, &fw_main); + stage = load_stage(&ctx, ROMSTAGE_INDEX, &fw_main, &fw_info); + if (stage == NULL) { + VBDEBUG("Failed to load stage\n"); + reboot(); + } + save_if_needed(&ctx); + if (rv) { + VBDEBUG("Reboot requested (%x)\n", rv); + reboot(); + } + + /* TODO: Do we need to lock secdata? */ + VBDEBUG("Locking TPM\n"); + + /* Load next stage and jump to it */ + VBDEBUG("Jumping to rw-romstage @%llx\n", stage->entry); + enter_stage(stage); + + /* Shouldn't reach here */ + VBDEBUG("Halting\n"); + for (;;); +} -- cgit v1.2.3