From 1a3ae36c6abcf826e9ca7b980c81a465e53deb0a Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Tue, 24 Nov 2020 22:30:52 +0800 Subject: mb/google/zork/var/vliboz: Add LTE_RST power sequence Latest HW schematic add LTE_RST pin to control module power sequence. BUG=b:173490220 BRANCH=zork TEST=measure the waveform is meet the LTE module spec. Signed-off-by: Eric Lai Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/zork/variants/vilboz/gpio.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/zork/variants/vilboz/gpio.c b/src/mainboard/google/zork/variants/vilboz/gpio.c index 6fba0e2595..c6ef161647 100644 --- a/src/mainboard/google/zork/variants/vilboz/gpio.c +++ b/src/mainboard/google/zork/variants/vilboz/gpio.c @@ -19,6 +19,8 @@ static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = { static const struct soc_amd_gpio vilboz_gpio_set_stage_ram[] = { /* P sensor INT */ PAD_INT(GPIO_40, PULL_NONE, LEVEL_LOW, STATUS_DELIVERY), + /* LTE_RST_L */ + PAD_GPO(GPIO_89, HIGH), }; const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) -- cgit v1.2.3