From 1985894e74711934018f97d082f0b9a9db230894 Mon Sep 17 00:00:00 2001
From: Wenbin Mei <wenbin.mei@mediatek.com>
Date: Fri, 25 Sep 2020 10:03:02 +0800
Subject: soc/mediatek/mt8192: ufs: Disable reference clock

UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
---
 src/soc/mediatek/mt8192/Makefile.inc             |  1 +
 src/soc/mediatek/mt8192/include/soc/addressmap.h |  1 +
 src/soc/mediatek/mt8192/include/soc/ufs.h        | 17 +++++++++++++++++
 src/soc/mediatek/mt8192/soc.c                    |  2 ++
 src/soc/mediatek/mt8192/ufs.c                    |  9 +++++++++
 5 files changed, 30 insertions(+)
 create mode 100644 src/soc/mediatek/mt8192/include/soc/ufs.h
 create mode 100644 src/soc/mediatek/mt8192/ufs.c

(limited to 'src')

diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc
index 23799663d7..cf09b3cf65 100644
--- a/src/soc/mediatek/mt8192/Makefile.inc
+++ b/src/soc/mediatek/mt8192/Makefile.inc
@@ -55,6 +55,7 @@ ramstage-y += spm.c
 ramstage-y += sspm.c
 ramstage-y += ../common/timer.c
 ramstage-y += ../common/uart.c
+ramstage-y += ufs.c
 ramstage-y += ../common/usb.c usb.c
 
 MT8192_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8192
diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h
index c9b39076b1..7660bccac1 100644
--- a/src/soc/mediatek/mt8192/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h
@@ -49,6 +49,7 @@ enum {
 	SPI7_BASE		= IO_PHYS + 0x0101E000,
 	SSUSB_IPPC_BASE		= IO_PHYS + 0x01203e00,
 	SFLASH_REG_BASE		= IO_PHYS + 0x01234000,
+	UFSHCI_BASE		= IO_PHYS + 0x01270000,
 	EFUSEC_BASE		= IO_PHYS + 0x01C10000,
 	IOCFG_RM_BASE		= IO_PHYS + 0x01C20000,
 	I2C_BASE		= IO_PHYS + 0x01CB0000,
diff --git a/src/soc/mediatek/mt8192/include/soc/ufs.h b/src/soc/mediatek/mt8192/include/soc/ufs.h
new file mode 100644
index 0000000000..70a30a9a06
--- /dev/null
+++ b/src/soc/mediatek/mt8192/include/soc/ufs.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8192_UFS_H
+#define SOC_MEDIATEK_MT8192_UFS_H
+
+#include <device/mmio.h>
+#include <soc/addressmap.h>
+
+void ufs_disable_refclk(void);
+
+enum ufshci_offset {
+	REG_UFS_REFCLK_CTRL = 0x144,
+};
+
+#define UFS_REFCLK_CTRL	(UFSHCI_BASE + REG_UFS_REFCLK_CTRL)
+
+#endif /* SOC_MEDIATEK_MT8192_UFS_H */
diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c
index bf9e8e794e..8696f342d4 100644
--- a/src/soc/mediatek/mt8192/soc.c
+++ b/src/soc/mediatek/mt8192/soc.c
@@ -5,6 +5,7 @@
 #include <soc/mcupm.h>
 #include <soc/mmu_operations.h>
 #include <soc/sspm.h>
+#include <soc/ufs.h>
 #include <symbols.h>
 
 static void soc_read_resources(struct device *dev)
@@ -17,6 +18,7 @@ static void soc_init(struct device *dev)
 	mtk_mmu_disable_l2c_sram();
 	mcupm_init();
 	sspm_init();
+	ufs_disable_refclk();
 }
 
 static struct device_operations soc_ops = {
diff --git a/src/soc/mediatek/mt8192/ufs.c b/src/soc/mediatek/mt8192/ufs.c
new file mode 100644
index 0000000000..2537fa7883
--- /dev/null
+++ b/src/soc/mediatek/mt8192/ufs.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ufs.h>
+
+void ufs_disable_refclk(void)
+{
+	/* disable ref clock to let UFSHCI release SPM signal */
+	write32((void *)UFS_REFCLK_CTRL, 0);
+}
-- 
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