From 174755f55528188ec69efe2836944c6c28e5a976 Mon Sep 17 00:00:00 2001 From: Saurabh Mishra Date: Mon, 2 Sep 2024 13:39:55 +0530 Subject: soc/intel/common/block: Include register offsets for POWER_CTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Details: - Add (POWER_CTL) – Offset 0x1fc required bits. Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71 Signed-off-by: Saurabh Mishra Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Pratikkumar V Prajapati --- src/soc/intel/common/block/include/intelblocks/msr.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 158cc9e3fe..a03032899d 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -50,7 +50,10 @@ #define PRMRR_PHYS_MASK_VALID (1 << 11) #define MSR_PRMRR_VALID_CONFIG 0x1fb #define MSR_POWER_CTL 0x1fc +#define ENABLE_BIDIR_PROCHOT (1 << 0) #define POWER_CTL_C1E_MASK (1 << 1) +#define PWR_PERF_PLATFORM_OVR (1 << 18) +#define VR_THERM_ALERT_DISABLE_LOCK (1 << 23) #define MSR_PRMRR_BASE_0 0x2a0 #define MSR_EVICT_CTL 0x2e0 #define MSR_LT_CONTROL 0x2e7 -- cgit v1.2.3