From 16fe1e0246df10fd9bac30c091b38d454d96cc89 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 22 Jul 2020 16:12:33 +0200 Subject: nb/intel/ironlake: Drop `D0F0_` prefix from register names Only some registers have such a prefix. Drop it for consistency. Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43731 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/lenovo/t410/romstage.c | 6 ++--- src/northbridge/intel/ironlake/early_init.c | 2 +- src/northbridge/intel/ironlake/hostbridge_regs.h | 22 ++++++++-------- src/northbridge/intel/ironlake/northbridge.c | 10 ++++---- src/northbridge/intel/ironlake/raminit.c | 32 ++++++++++++------------ 5 files changed, 36 insertions(+), 36 deletions(-) (limited to 'src') diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 6856f5b3d9..445ef7afc0 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -32,7 +32,7 @@ static void hybrid_graphics_init(void) early_hybrid_graphics(&igd, &peg); /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN); + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); if (peg) @@ -42,9 +42,9 @@ static void hybrid_graphics_init(void) reg32 |= DEVEN_IGD; else /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), D0F0_GGC, 2); + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, reg32); + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); } void mainboard_pre_raminit(void) diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index 34ae6c1d19..b68d954849 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -102,7 +102,7 @@ void ironlake_early_initialization(int chipset_type) elog_boot_notify(s3_resume); /* Device Enable */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); early_cpu_init(); diff --git a/src/northbridge/intel/ironlake/hostbridge_regs.h b/src/northbridge/intel/ironlake/hostbridge_regs.h index cd865aae73..b835736e4c 100644 --- a/src/northbridge/intel/ironlake/hostbridge_regs.h +++ b/src/northbridge/intel/ironlake/hostbridge_regs.h @@ -5,8 +5,8 @@ #define EPBAR 0x40 #define MCHBAR 0x48 -#define D0F0_GGC 0x52 -#define D0F0_DEVEN 0x54 +#define GGC 0x52 +#define DEVEN 0x54 #define DEVEN_IGD (1 << 3) #define DEVEN_PEG10 (1 << 1) #define DEVEN_HOST (1 << 0) @@ -16,17 +16,17 @@ #define LAC 0x87 /* Legacy Access Control */ -#define D0F0_REMAPBASE 0x98 -#define D0F0_REMAPLIMIT 0x9a -#define D0F0_TOM 0xa0 -#define D0F0_TOUUD 0xa2 -#define D0F0_IGD_BASE 0xa4 -#define D0F0_GTT_BASE 0xa8 +#define REMAPBASE 0x98 +#define REMAPLIMIT 0x9a +#define TOM 0xa0 +#define TOUUD 0xa2 +#define IGD_BASE 0xa4 +#define GTT_BASE 0xa8 #define TSEG 0xac /* TSEG base */ -#define D0F0_TOLUD 0xb0 +#define TOLUD 0xb0 -#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define SKPD 0xdc /* Scratchpad Data */ -#define D0F0_CAPID0 0xe0 +#define CAPID0 0xe0 #endif /* __IRONLAKE_HOSTBRIDGE_REGS_H__ */ diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 4cd098ce92..b99e2d5b43 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -103,7 +103,7 @@ static void mc_read_resources(struct device *dev) tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG); touud = pci_read_config16(pcidev_on_root(0, 0), - D0F0_TOUUD); + TOUUD); printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud); @@ -114,7 +114,7 @@ static void mc_read_resources(struct device *dev) mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); - reg16 = pci_read_config16(pcidev_on_root(0, 0), D0F0_GGC); + reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; /* Igd memory */ @@ -128,9 +128,9 @@ static void mc_read_resources(struct device *dev) uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; igd_base = - pci_read_config32(pcidev_on_root(0, 0), D0F0_IGD_BASE); + pci_read_config32(pcidev_on_root(0, 0), IGD_BASE); gtt_base = - pci_read_config32(pcidev_on_root(0, 0), D0F0_GTT_BASE); + pci_read_config32(pcidev_on_root(0, 0), GTT_BASE); mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); @@ -183,7 +183,7 @@ static void ironlake_init(void *const chip_info) } const struct device *const d0f0 = pcidev_on_root(0, 0); if (d0f0) - pci_update_config32(d0f0, D0F0_DEVEN, deven_mask, 0); + pci_update_config32(d0f0, DEVEN, deven_mask, 0); } diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 8b28e51394..c30a5dcf12 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -1380,7 +1380,7 @@ static void program_total_memory_map(struct raminfo *info) memset(memory_map, 0, sizeof(memory_map)); if (info->uma_enabled) { - u16 t = pci_read_config16(NORTHBRIDGE, D0F0_GGC); + u16 t = pci_read_config16(NORTHBRIDGE, GGC); gav(t); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; @@ -1433,17 +1433,17 @@ static void program_total_memory_map(struct raminfo *info) tseg_base -= quickpath_reserved; tseg_base = ALIGN_DOWN(tseg_base, 8); - pci_write_config16(NORTHBRIDGE, D0F0_TOLUD, tolud << 4); - pci_write_config16(NORTHBRIDGE, D0F0_TOM, tom >> 6); + pci_write_config16(NORTHBRIDGE, TOLUD, tolud << 4); + pci_write_config16(NORTHBRIDGE, TOM, tom >> 6); if (memory_remap) { - pci_write_config16(NORTHBRIDGE, D0F0_REMAPBASE, remap_base >> 6); - pci_write_config16(NORTHBRIDGE, D0F0_REMAPLIMIT, (touud - 64) >> 6); + pci_write_config16(NORTHBRIDGE, REMAPBASE, remap_base >> 6); + pci_write_config16(NORTHBRIDGE, REMAPLIMIT, (touud - 64) >> 6); } - pci_write_config16(NORTHBRIDGE, D0F0_TOUUD, touud); + pci_write_config16(NORTHBRIDGE, TOUUD, touud); if (info->uma_enabled) { - pci_write_config32(NORTHBRIDGE, D0F0_IGD_BASE, uma_base_igd << 20); - pci_write_config32(NORTHBRIDGE, D0F0_GTT_BASE, uma_base_gtt << 20); + pci_write_config32(NORTHBRIDGE, IGD_BASE, uma_base_igd << 20); + pci_write_config32(NORTHBRIDGE, GTT_BASE, uma_base_gtt << 20); } pci_write_config32(NORTHBRIDGE, TSEG, tseg_base << 20); @@ -1480,7 +1480,7 @@ static void collect_system_info(struct raminfo *info) for (i = 0; i < 3; i++) gav(capid0[i] = - pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 | (i << 2))); + pci_read_config32(NORTHBRIDGE, CAPID0 | (i << 2))); gav(info->revision = pci_read_config8(NORTHBRIDGE, PCI_REVISION_ID)); info->max_supported_clock_speed_index = (~capid0[1] & 7); @@ -1488,7 +1488,7 @@ static void collect_system_info(struct raminfo *info) info->uma_enabled = 0; else gav(info->uma_enabled = - pci_read_config8(NORTHBRIDGE, D0F0_DEVEN) & 8); + pci_read_config8(NORTHBRIDGE, DEVEN) & 8); /* Unrecognised: [0000:fffd3d2d] 37f81.37f82 ! CPUID: eax: 00000001; ecx: 00000e00 => 00020655.00010800.029ae3ff.bfebfbff */ info->silicon_revision = 0; @@ -1823,7 +1823,7 @@ static void setup_heci_uma(struct raminfo *info) info->memory_reserved_for_heci_mb = reg44 & 0x3f; info->heci_uma_addr = ((u64) - ((((u64) pci_read_config16(NORTHBRIDGE, D0F0_TOM)) << 6) - + ((((u64) pci_read_config16(NORTHBRIDGE, TOM)) << 6) - info->memory_reserved_for_heci_mb)) << 20; pci_read_config32(NORTHBRIDGE, DMIBAR); @@ -3669,10 +3669,10 @@ void chipset_init(const int s3resume) ggc = 0xb00 | ((gfxsize + 5) << 4); - pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc | 2); + pci_write_config16(NORTHBRIDGE, GGC, ggc | 2); u16 deven; - deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); // = 0x3 + deven = pci_read_config16(NORTHBRIDGE, DEVEN); // = 0x3 if (deven & 8) { MCHBAR8(0x2c30) = 0x20; @@ -3690,7 +3690,7 @@ void chipset_init(const int s3resume) MCHBAR32_AND_OR(0x30, 0, 0x40); - pci_write_config16(NORTHBRIDGE, D0F0_GGC, ggc); + pci_write_config16(NORTHBRIDGE, GGC, ggc); gav(read32(DEFAULT_RCBA + 0x3428)); write32(DEFAULT_RCBA + 0x3428, 0x1d); } @@ -3708,7 +3708,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) printk(RAM_DEBUG, "Scratchpad MCHBAR8(0x2ca8): 0x%04x\n", x2ca8); - deven = pci_read_config16(NORTHBRIDGE, D0F0_DEVEN); + deven = pci_read_config16(NORTHBRIDGE, DEVEN); memset(&info, 0x5a, sizeof(info)); @@ -3836,7 +3836,7 @@ void raminit(const int s3resume, const u8 *spd_addrmap) gav(0x55); - gav(pci_read_config32(NORTHBRIDGE, D0F0_CAPID0 + 4)); + gav(pci_read_config32(NORTHBRIDGE, CAPID0 + 4)); } /* after SPD */ -- cgit v1.2.3