From 16ebc9831f156a03bd5ecd21e9365c09bfc43554 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Thu, 23 Aug 2018 12:01:12 +0200 Subject: siemens/mc_apl1: Select DDR50 mode for eMMC To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed to DDR50 mode. Change-Id: I40658b44a99e6600ed00950a1a177961f0055e7a Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/28283 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index a273a5983f..f3e8a77143 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -43,6 +43,9 @@ chip soc/intel/apollolake # [6:0] steps of delay for HS200, each 125ps. register "emmc_rx_cmd_data_cntl2" = "0x10008" + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "2" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- cgit v1.2.3