From 15fa992cc8467b4cbd8ebea62e3e4c947827137e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 10:00:28 +0300 Subject: intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/model_6ex/cache_as_ram.inc | 10 ++++++++-- src/cpu/intel/socket_BGA956/Makefile.inc | 1 + src/cpu/intel/socket_LGA771/Makefile.inc | 1 + src/cpu/intel/socket_LGA775/Makefile.inc | 1 + src/cpu/intel/socket_mFCPGA478/Makefile.inc | 1 + src/mainboard/apple/macbook21/romstage.c | 2 +- src/mainboard/asus/dsbf/romstage.c | 4 ++-- src/mainboard/getac/p470/romstage.c | 4 ++-- src/mainboard/ibase/mb899/romstage.c | 4 ++-- src/mainboard/intel/eagleheights/romstage.c | 4 ++-- src/mainboard/kontron/986lcd-m/romstage.c | 4 ++-- src/mainboard/lenovo/t400/romstage.c | 4 ++-- src/mainboard/lenovo/t60/romstage.c | 4 ++-- src/mainboard/lenovo/x200/romstage.c | 4 ++-- src/mainboard/lenovo/x60/romstage.c | 4 ++-- src/mainboard/roda/rk886ex/romstage.c | 4 ++-- src/mainboard/roda/rk9/romstage.c | 4 ++-- src/mainboard/supermicro/x7db8/romstage.c | 4 ++-- 18 files changed, 37 insertions(+), 27 deletions(-) (limited to 'src') diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 2eb824cea7..f4c4af86d3 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -132,7 +132,12 @@ clear_mtrrs: post_code(0x23) /* Call romstage.c main function. */ - call main + call romstage_main + + /* Save return value from romstage_main. It contains the stack to use + * after cache-as-ram is torn down. It also contains the information + * for setting up MTRRs. */ + movl %eax, %ebx post_code(0x2f) @@ -219,7 +224,8 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */ - movl $CONFIG_RAMTOP, %esp + /* Setup stack as indicated by return value from romstage_main(). */ + movl %ebx, %esp movl %esp, %ebp call copy_and_run diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 2325bb9e32..22c1a7c9eb 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -10,3 +10,4 @@ subdirs-y += ../speedstep # Use Intel Core (not Core 2) code for CAR init, any CPU might be used. cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_LGA771/Makefile.inc b/src/cpu/intel/socket_LGA771/Makefile.inc index 8235fc52aa..d0a5b63264 100644 --- a/src/cpu/intel/socket_LGA771/Makefile.inc +++ b/src/cpu/intel/socket_LGA771/Makefile.inc @@ -9,3 +9,4 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 54a762eb44..371a801425 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -16,3 +16,4 @@ subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc romstage-y += ../car/romstage.c +romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_mFCPGA478/Makefile.inc b/src/cpu/intel/socket_mFCPGA478/Makefile.inc index 749f6abf06..6056d3c453 100644 --- a/src/cpu/intel/socket_mFCPGA478/Makefile.inc +++ b/src/cpu/intel/socket_mFCPGA478/Makefile.inc @@ -12,3 +12,4 @@ subdirs-y += ../hyperthreading subdirs-y += ../speedstep cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc +romstage-y += ../car/romstage.c diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 05a11a615e..296f8986b3 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -278,7 +278,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x51, 0x52, 0x53 }; diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index 7f2e9ea5f4..45ca046748 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -105,8 +106,7 @@ int mainboard_set_fbd_clock(int speed) } } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) enable_lapic(); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 9db19be51c..396a2ecb84 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -259,8 +260,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index b472ba4338..9d2b90ac0d 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -217,8 +218,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 47675a5317..c254f17b7e 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" @@ -117,8 +118,7 @@ static void early_config(void) pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { /* int boot_mode = 0; */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 80bcdcb60d..3dcf4cc54e 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -28,6 +28,7 @@ #include "option_table.h" #include #include +#include #include #include #include @@ -323,8 +324,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 16676faa02..dbec8d0e90 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -23,13 +23,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) @@ -67,7 +67,7 @@ static void early_lpc_setup(void) pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); } -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index ef86e51142..3ed6afde6d 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -199,8 +200,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; int dock_err; diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 91500f4774..7d4bc61f9a 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -23,13 +23,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) @@ -67,7 +67,7 @@ static void early_lpc_setup(void) pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); } -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index a60e05678d..1f249a624a 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include #include @@ -206,8 +207,7 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 }; diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index fb06695504..f3af5fa6a0 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -244,8 +245,7 @@ static void init_artec_dongle(void) outb(0xf4, 0x88); } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { int s3resume = 0; diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index ca384260fe..cad75aee1b 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -115,8 +116,7 @@ static void default_superio_gpio_setup(void) outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */ } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index 71ae64d327..ac8da6d8a6 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include #include @@ -106,8 +107,7 @@ int mainboard_set_fbd_clock(int speed) } } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) enable_lapic(); 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