From 12a1fc2939879d3ba3863619d8ab2e5f152e392c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 21 Aug 2023 11:12:04 +0200 Subject: soc/intel/alderlake: Guard PchPcie{Clock,Power}Gating on RPL FSP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PchPcieClockGating and PchPciePowerGating UPDs are not yet available in RPL-S IOT FSP. It also looks like those UPDs are not generally available in all public RaptorLake FSP headers yet, so guard it against SOC_INTEL_RAPTORLAKE to avoid build errors. Change-Id: Iedac21bafa3428957e054fc8fefa38f9f776772d Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/77337 Reviewed-by: Jan Samek Tested-by: build bot (Jenkins) Reviewed-by: Lean Sheng Tan --- src/soc/intel/alderlake/fsp_params.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 402af89ed8..67fb55bb7d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -924,7 +924,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); -#if CONFIG(FSP_TYPE_IOT) +#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_RAPTORLAKE) /* * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 -- cgit v1.2.3