From 0f633f7f7f1ff38f9f55d98fd0c5e5c26b2a2e07 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 22 Nov 2022 11:40:01 +0100 Subject: mb/siemens/mc_ehl2: Enable downshift for Marvell PHYs Set downshift counter to 2 for all Marvell PHYs on this mainboard before the PHY downshifts to the next highest speed. Change-Id: I32b5f25a3e1e0f962dff3110143e236992ef8e7d Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/69887 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 8090927661..e1c297274c 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -191,6 +191,7 @@ chip soc/intel/elkhartlake register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 0 on # PHY address ops m88e1512_ops end @@ -206,6 +207,7 @@ chip soc/intel/elkhartlake register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 1 on # PHY address ops m88e1512_ops end @@ -224,6 +226,7 @@ chip soc/intel/elkhartlake register "led_1_ctrl" = "1" # INTn is routed to LED[2] pin register "enable_int" = "true" + register "downshift_cnt" = "2" device mdio 1 on # PHY address ops m88e1512_ops end -- cgit v1.2.3