From 0cdcdc736ea28be7bfc6eabdac2430ecf6ee409c Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Tue, 8 Jun 2021 23:41:15 -0700 Subject: soc/intel/elkhartlake: Update FSP-S FuSa related settings Further add initial Silicon UPD settings for FuSa (Functional Safety). Disable all by default, due to FSP binary enable all by default. Signed-off-by: Lean Sheng Tan Change-Id: I88264ba3e3f9f54ad949c55b230082d1fa289fa4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55342 Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- src/soc/intel/elkhartlake/chip.h | 3 +++ src/soc/intel/elkhartlake/fsp_params.c | 8 ++++++++ 2 files changed, 11 insertions(+) (limited to 'src') diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 3df1ece8e0..c2faddc2b9 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -68,6 +68,9 @@ struct soc_intel_elkhartlake_config { /* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */ bool MemoryThermalThrottlingDisable; + /* FuSa (Functional Safety): Disable - Default (0) / Enable (1) */ + bool FuSaEnable; + /* System Agent dynamic frequency support. * When enabled memory will be trained at different frequencies. * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2 diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 213fc8c7f1..2a8b07e45f 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -344,6 +344,14 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchFivrVccinAuxOffToHighCurModeVolTranTime = 0x0096; params->FivrSpreadSpectrum = 0xF; + /* FuSa (Functional Safety) config */ + if (!config->FuSaEnable) { + params->DisplayFusaConfigEnable = 0; + params->GraphicFusaConfigEnable = 0; + params->OpioFusaConfigEnable = 0; + params->PsfFusaConfigEnable = 0; + } + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- cgit v1.2.3