From 0ca3a0792d550ef75b3a1b207f4bf04eb83e507f Mon Sep 17 00:00:00 2001 From: Edward Hill Date: Tue, 18 Dec 2018 20:19:36 -0700 Subject: amd/stoneyridge: Clear SMI_EVENT_STATUS when entering S3/S5 disable_all_smi_status() was not clearing SMI_EVENT_STATUS. This caused us to complain in the eventlog (ELOG_SLEEP_PENDING_GPE0_WAKE) and then wake early from sleep when waiting for a cr50 reset to turn on a cr50 update. BUG=b:121203745 TEST=Careena remains in S5 until cr50 reset after cr50 update, and ELOG_SLEEP_PENDING_GPE0_WAKE is no longer seen in eventlog. Change-Id: I2eec014109249d5c3574c4dbdec5569e2a0bfc8e Signed-off-by: Edward Hill Reviewed-on: https://review.coreboot.org/c/30304 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Reviewed-by: Martin Roth --- src/soc/amd/stoneyridge/smihandler.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index a662bc5d37..4854e52553 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -113,6 +113,7 @@ static void sb_apmc_smi_handler(void) static void disable_all_smi_status(void) { smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); + smi_write32(SMI_EVENT_STATUS, smi_read32(SMI_EVENT_STATUS)); smi_write32(SMI_REG_SMISTS0, smi_read32(SMI_REG_SMISTS0)); smi_write32(SMI_REG_SMISTS1, smi_read32(SMI_REG_SMISTS1)); smi_write32(SMI_REG_SMISTS2, smi_read32(SMI_REG_SMISTS2)); -- cgit v1.2.3