From 0b39a5a23ac8eb06b06757b94f641151d8603c10 Mon Sep 17 00:00:00 2001 From: Werner Zeh Date: Fri, 23 Jul 2021 13:09:41 +0200 Subject: mb/siemens/mc_ehl1: Disable LTR for all PCIe root ports Latency Tolerance Reporting is yet another PCIe power management feature which can have a bad influence on realtime performance. Disable this feature for all PCIe root ports. Change-Id: I38023e095ca55efd2178ad944f651fee1f1c34cd Signed-off-by: Werner Zeh Reviewed-on: https://review.coreboot.org/c/coreboot/+/56595 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src') diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index d1c5c82b2e..f05f025e8b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -77,6 +77,14 @@ chip soc/intel/elkhartlake register "PcieRpL1Substates[4]" = "L1_SS_DISABLED" register "PcieRpL1Substates[5]" = "L1_SS_DISABLED" + # Disable LTR for all PCIe root ports + register "PcieRpLtrDisable[0]" = "true" + register "PcieRpLtrDisable[1]" = "true" + register "PcieRpLtrDisable[2]" = "true" + register "PcieRpLtrDisable[3]" = "true" + register "PcieRpLtrDisable[4]" = "true" + register "PcieRpLtrDisable[5]" = "true" + # Storage (SATA/SDCARD/EMMC) related UPDs register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" -- cgit v1.2.3