From 09ccd418f40bad87098e71411e408bf9b5c69881 Mon Sep 17 00:00:00 2001 From: Arthur Heymans <arthur@aheymans.xyz> Date: Mon, 3 Jun 2019 19:36:25 +0200 Subject: sb/intel/common: Link SPI code in bootblock Change-Id: I2874bc37c6bceb2b22115a09ed1501ce917b4623 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> --- src/southbridge/intel/common/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 4cf6e6f57e..deab85ff97 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -45,6 +45,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c -- cgit v1.2.3