From 099bec1cc613b8fd9cd166914bbcc3d9e46d4df5 Mon Sep 17 00:00:00 2001 From: Hualin Wei Date: Fri, 1 Nov 2024 11:37:56 +0800 Subject: mb/google/dedede/var/awasuki: Enable LTR mechanism for PCIe root port 8 Realtek AX generation IC utilizes LTR-issued latency requests to optimize WiFi latency and power consumption, it requires host enabling LTR to meet the design requirement. We enabled the host's LTR by enabling PCIe root port 8, which met resltek's technical requirements. BUG=b:366383364 TEST=Tested on Awasuki with RTL8852BE Use command $ lspci -vv, LTR+ is listed on DevCtl2 Change-Id: I0c80f89b4fdb52a5d9da17548537072ec2d40418 Signed-off-by: Hualin Wei Reviewed-on: https://review.coreboot.org/c/coreboot/+/84951 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Weimin Wu Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/awasuki/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb index cc7eba8330..e0abe19443 100644 --- a/src/mainboard/google/dedede/variants/awasuki/overridetree.cb +++ b/src/mainboard/google/dedede/variants/awasuki/overridetree.cb @@ -1,4 +1,7 @@ chip soc/intel/jasperlake + # PCIe RP LTR configuration + register "PcieRpLtrEnable[7]" = "1" + # USB Port Configuration register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[3]" = "USB2_PORT_EMPTY" -- cgit v1.2.3