From 0948b363b0568e70af2352566dee39e0df82d96d Mon Sep 17 00:00:00 2001
From: Frans Hendriks <fhendriks@eltan.com>
Date: Thu, 19 Nov 2020 15:13:02 +0100
Subject: soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T output

Report the FSP temporary RAM location

Tested on Facebook FBG1701

Change-Id: Ia2ce48f7a7948d1fe51ad1ca33b8fb385674cb41
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
 src/soc/intel/braswell/bootblock/bootblock.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src')

diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index 10ac02584d..ae1c97a9c4 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -5,6 +5,7 @@
 #include <build.h>
 #include <console/console.h>
 #include <device/pci_ops.h>
+#include <fsp/util.h>
 #include <pc80/mc146818rtc.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
@@ -117,6 +118,8 @@ void bootblock_soc_early_init(void)
 }
 void bootblock_soc_init(void)
 {
+	report_fsp_output();
+
 	/* Continue chipset initialization */
 	soc_rtc_init();
 	set_max_freq();
-- 
cgit v1.2.3