From 07190470053f1e4f937a0d0d100859c452c00fbc Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 17 Mar 2010 17:50:48 +0000 Subject: fix HPET on some ICH southbridges Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/intel/i82801ax/i82801ax_lpc.c | 25 ------------------------- src/southbridge/intel/i82801bx/i82801bx_lpc.c | 25 ------------------------- src/southbridge/intel/i82801dx/i82801dx_lpc.c | 24 ------------------------ src/southbridge/intel/i82801ex/i82801ex_lpc.c | 1 + 4 files changed, 1 insertion(+), 74 deletions(-) (limited to 'src') diff --git a/src/southbridge/intel/i82801ax/i82801ax_lpc.c b/src/southbridge/intel/i82801ax/i82801ax_lpc.c index 590f057ef7..e42bac3449 100644 --- a/src/southbridge/intel/i82801ax/i82801ax_lpc.c +++ b/src/southbridge/intel/i82801ax/i82801ax_lpc.c @@ -272,28 +272,6 @@ static void i82801ax_lpc_decode_en(device_t dev, uint16_t ich_model) } } -static void enable_hpet(struct device *dev) -{ -#ifdef HPET_PRESENT - uint32_t reg32; - uint32_t code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - /* TODO: reg32 is never written to anywhere? */ - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); -#endif -} - static void lpc_init(struct device *dev) { uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); @@ -326,9 +304,6 @@ static void lpc_init(struct device *dev) /* Setup decode ports and LPC I/F enables. */ i82801ax_lpc_decode_en(dev, ich_model); - - /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(dev); } static void i82801ax_lpc_read_resources(device_t dev) diff --git a/src/southbridge/intel/i82801bx/i82801bx_lpc.c b/src/southbridge/intel/i82801bx/i82801bx_lpc.c index 4691ed4137..0d7e09c931 100644 --- a/src/southbridge/intel/i82801bx/i82801bx_lpc.c +++ b/src/southbridge/intel/i82801bx/i82801bx_lpc.c @@ -272,28 +272,6 @@ static void i82801bx_lpc_decode_en(device_t dev, uint16_t ich_model) } } -static void enable_hpet(struct device *dev) -{ -#ifdef HPET_PRESENT - uint32_t reg32; - uint32_t code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - /* TODO: reg32 is never written to anywhere? */ - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); -#endif -} - static void lpc_init(struct device *dev) { uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID); @@ -326,9 +304,6 @@ static void lpc_init(struct device *dev) /* Setup decode ports and LPC I/F enables. */ i82801bx_lpc_decode_en(dev, ich_model); - - /* Initialize the High Precision Event Timers, if present. */ - enable_hpet(dev); } static void i82801bx_lpc_read_resources(device_t dev) diff --git a/src/southbridge/intel/i82801dx/i82801dx_lpc.c b/src/southbridge/intel/i82801dx/i82801dx_lpc.c index 181f5454e1..8f698ee53d 100644 --- a/src/southbridge/intel/i82801dx/i82801dx_lpc.c +++ b/src/southbridge/intel/i82801dx/i82801dx_lpc.c @@ -177,27 +177,6 @@ static void i82801dx_lpc_decode_en(device_t dev) pci_write_config16(dev, LPC_EN, 0x300F); } -static void enable_hpet(struct device *dev) -{ - u32 reg32; - u32 code = (0 & 0x3); - - reg32 = pci_read_config32(dev, GEN_CNTL); - reg32 |= (1 << 17); /* Enable HPET. */ - /* - * Bits [16:15] Memory Address Range - * 00 FED0_0000h - FED0_03FFh - * 01 FED0_1000h - FED0_13FFh - * 10 FED0_2000h - FED0_23FFh - * 11 FED0_3000h - FED0_33FFh - */ - reg32 &= ~(3 << 15); /* Clear it */ - reg32 |= (code << 15); - pci_write_config32(dev, GEN_CNTL, reg32); - - printk_debug("Enabling HPET @0x%x\n", HPET_ADDR | (code << 12)); -} - static void lpc_init(struct device *dev) { /* Set the value for PCI command register. */ @@ -228,9 +207,6 @@ static void lpc_init(struct device *dev) /* Setup decode ports and LPC I/F enables. */ i82801dx_lpc_decode_en(dev); - - /* Initialize the High Precision Event Timers */ - enable_hpet(dev); } static void i82801dx_lpc_read_resources(device_t dev) diff --git a/src/southbridge/intel/i82801ex/i82801ex_lpc.c b/src/southbridge/intel/i82801ex/i82801ex_lpc.c index a8b48ae454..b9d19074a4 100644 --- a/src/southbridge/intel/i82801ex/i82801ex_lpc.c +++ b/src/southbridge/intel/i82801ex/i82801ex_lpc.c @@ -231,6 +231,7 @@ static void enable_hpet(struct device *dev) dword &= ~(3 << 15); /* clear it */ dword |= (code<<15); + pci_write_config32(dev, GEN_CNTL, dword); printk_debug("enabling HPET @0x%lx\n", hpet_address | (code <<12) ); } -- cgit v1.2.3