From 06eecfea969649202b4a20381f4d24db4eb9d3bd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 10 Jun 2021 15:33:56 +0200 Subject: soc/intel/denverton_ns: Remove SOC specific FSP location overrides MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1) FSP-S should not run XIP 2) Overriding the FSP-T location conflicts with the location set in drivers/intel/fsp2_0 This fixes a regression caused by commit 0f068a600e (drivers/intel/fsp2_0: Fix the FSP-T position) Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/G6WRFITANOS2JEYG3GKB2ZNVCLUZ6W7P/ Change-Id: I381781c1de7c6dad32d66b295c927419dea7d8be Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/55389 Tested-by: build bot (Jenkins) Reviewed-by: Mariusz Szafrański Reviewed-by: King Sumo Reviewed-by: Angel Pons --- src/soc/intel/denverton_ns/Kconfig | 23 ++--------------------- src/soc/intel/denverton_ns/Makefile.inc | 5 ----- 2 files changed, 2 insertions(+), 26 deletions(-) (limited to 'src') diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index f6bafae861..ee8e9eb2b2 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -41,31 +41,12 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS + select FSP_T_XIP if FSP_CAR + select FSP_M_XIP config MMCONF_BASE_ADDRESS default 0xe0000000 -config FSP_T_ADDR - hex "Intel FSP-T (temp RAM init) binary location" - depends on ADD_FSP_BINARIES && FSP_CAR - default 0xfff30000 - help - The memory location of the Intel FSP-T binary for this platform. - -config FSP_M_ADDR - hex "Intel FSP-M (memory init) binary location" - depends on ADD_FSP_BINARIES - default 0xfff32000 - help - The memory location of the Intel FSP-M binary for this platform. - -config FSP_S_ADDR - hex "Intel FSP-S (silicon init) binary location" - depends on ADD_FSP_BINARIES - default 0xfffc3000 - help - The memory location of the Intel FSP-S binary for this platform. - config FSP_HEADER_PATH default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index d8e18496d1..beb3471955 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -74,11 +74,6 @@ verstage-$(CONFIG_DRIVERS_UART_8250MEM) += uart_debug.c CPPFLAGS_common += -I$(src)/soc/intel/denverton_ns/include -##Set FSP binary blobs memory location -$(call strip_quotes,$(CONFIG_FSP_T_CBFS))-options := -b $(CONFIG_FSP_T_ADDR) --xip -$(call strip_quotes,$(CONFIG_FSP_M_CBFS))-options := -b $(CONFIG_FSP_M_ADDR) --xip -$(call strip_quotes,$(CONFIG_FSP_S_CBFS))-options := -b $(CONFIG_FSP_S_ADDR) --xip - cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5f-01 endif ## CONFIG_SOC_INTEL_DENVERTON_NS -- cgit v1.2.3