From 063e933194ec9b41775f5e2f1a175f1c97657f1b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 28 Sep 2020 17:55:02 +0530 Subject: soc/intel/skylake: Align PMC offset 0x31C name with CNL As per EDS PMC BASE Offset 0x31C is known as CPPMVRIC hence rename CIR31C with CPPMVRIC. Change-Id: Idaff62fb742e6c58b1d8e662b5e4087fa2da79a3 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/45795 Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/skylake/finalize.c | 4 ++-- src/soc/intel/skylake/include/soc/pmc.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 98f12a5b6c..0294a725b2 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -81,9 +81,9 @@ static void pch_finalize_script(struct device *dev) /* Disable XTAL shutdown qualification for low power idle. */ if (config->s0ix_enable) { - reg32 = read32(pmcbase + CIR31C); + reg32 = read32(pmcbase + CPPMVRIC); reg32 |= XTALSDQDIS; - write32(pmcbase + CIR31C, reg32); + write32(pmcbase + CPPMVRIC, reg32); } /* we should disable Heci1 based on the devicetree policy */ diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h index f4995a2e86..68d9eb3d27 100644 --- a/src/soc/intel/skylake/include/soc/pmc.h +++ b/src/soc/intel/skylake/include/soc/pmc.h @@ -82,6 +82,6 @@ #define GPE0_DW_SHIFT(x) (4*(x)) #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 -#define CIR31C 0x31c +#define CPPMVRIC 0x31c #define XTALSDQDIS (1 << 22) #endif -- cgit v1.2.3